DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,3-7,9-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ding et al., (Ding) US 2016/0365305 in view of Choi et al., (Choi) US 2020/0176342 and Moreno et al., (Moreno) US 2023/0137852.
Regarding claim 1, Ding shows in FIG.1-4, and discloses a semiconductor device comprising: a dielectric housing (170)[0015]; a semiconductor chip (110)[0015] disposed within the dielectric housing (170), the semiconductor chip (110) having first and second metal electrodes (145 on each sides)[0015] disposed on opposing surfaces thereof; a first lead frame (120)[0015] having a first end extending out of the dielectric housing (170) and having a second end terminating in a die pad (115) upon which the semiconductor chip (110) is mounted, a first quantity of solder (140) electrically connecting the die pad (115) to the first metal electrode (145) of the semiconductor chip (110); a second lead frame (135)[0015] having a first end extending out of the dielectric housing (170) and having a second end disposed adjacent the semiconductor chip (110); and a clip (125) having a first end connected to the second of the lead frame (135) and a second end extending over the semiconductor chip (110), wherein a bottom surface of the second end of the clip (125) includes a recess (groove in 125)[0021], a second quantity of solder (140) electrically connecting the clip (125) to the second metal electrode (145) of the semiconductor chip (110).
Ding differs from the claimed invention because he does not explicitly disclose a device wherein a top surface of the die pad includes a cavity having a first quantity of solder disposed therein; a clip having recess having a second quantity of solder disposed therein; wherein a top surface of the die pad is planar and includes a cavity defined by a lip extending outwardly from the top surface of the die pad, the cavity having a first quantity of solder disposed therein, and wherein the first quantity of solder electrically connecting connects the die pad to the first metal electrode of the semiconductor chip
Choi shows in FIG. 7,9, a device wherein a top surface of the die pad (111) includes a cavity having a first quantity of solder (140) [0050] disposed therein; a clip (160) a recess having a second quantity of solder (170) [0048] disposed therein.
Choi is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Ding. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Choi in the device of Ding because it will improve the electrical quality and reliability of the device [0051].
Moreno discloses a device wherein a top surface of the die pad (part of 859)[0062,0063] is planar and includes a cavity defined by a lip (extended portion of 859) extending outwardly from the top surface of the die pad, the cavity having a first quantity of solder (818)[0063] disposed therein, and wherein the first quantity of solder (818) electrically connecting connects the die pad to the first metal electrode (814 and metal under the chip) of the semiconductor chip.
Moreno is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Ding and Choi. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Moreno in the device of Ding and Choi because it will improve solder bridging and prevent the die from tilting [0063].
Regarding claim 3, Ding in view of Choi and Moreno discloses a semiconductor device, wherein the lip is rectangular (see Choi, FIG. 8).
Choi is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Ding. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Choi in the device of Ding because it will improve the electrical quality and reliability of the device [0051].
Regarding claim 4,5, Ding in view of Choi and Moreno discloses a semiconductor device, wherein the cavity has a depth in a range of 0.005 millimeters to 0.05 millimeters; wherein the recess has a depth in a range of 0.005 millimeters to 0.05 millimeters [Choi, 0007-0008].
Choi is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Ding. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Choi in the device of Ding because it will improve the electrical quality and reliability of the device [0051].
Regarding claim 6, Ding in view of Choi and Moreno discloses a semiconductor device, wherein the semiconductor chip is a transient voltage suppression device [0012].
Regarding claim 7, Ding in view of Choi and Moreno discloses a semiconductor device, wherein the clip (125, Ding) or (160, Choi) is L-shaped.
Regarding claim 9, Ding shows in FIG.1-4, a semiconductor device package comprising: a dielectric housing (170); a first lead frame (120) having a first end extending out of the dielectric housing (170) and having a second end terminating in a die pad (115) adapted to support a semiconductor chip (110), wherein a top surface of the die pad (115) includes a first quantity of solder (140) disposed therein; a second lead frame (135) having a first end extending out of the dielectric housing (170) and having a second end disposed within the dielectric housing; and a clip (125) having a first end connected to the second of the lead frame (135) and a second end adapted to be electrically connected to the semiconductor chip (110), wherein a bottom surface of the second end of the clip includes a recess (groove in 125)[0021] having a second quantity of solder.
Ding differs from the claimed invention because he does not explicitly disclose a device wherein a top surface of the die pad includes a cavity having a first quantity of solder disposed therein; a clip having recess having a second quantity of solder disposed therein; a device wherein a top surface of the die pad is planar and includes a cavity defined by a lip extending outwardly from the top surface of the die pad, the cavity having a first quantity of solder disposed therein.
Choi shows in FIG. 7,9, a device wherein a top surface of the die pad (111) includes a cavity having a first quantity of solder (140) [0050] disposed therein; a clip (160) a recess having a second quantity of solder (170) [0048] disposed therein.
Choi is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Ding. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Choi in the device of Ding because it will improve the electrical quality and reliability of the device [0051].
Moreno discloses a device wherein a top surface of the die pad (part of 859)[0062,0063] is planar and includes a cavity defined by a lip (extended portion of 859) extending outwardly from the top surface of the die pad, the cavity having a first quantity of solder (818)[0063] disposed therein.
Moreno is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Ding and Choi. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Moreno in the device of Ding and Choi because it will improve solder bridging and prevent the die from tilting [0063].
Regarding claim 11, Ding in view of Choi and Moreno discloses a semiconductor device, wherein the lip is rectangular (see Choi, FIG. 8).
Choi is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Ding. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Choi in the device of Ding because it will improve the electrical quality and reliability of the device [0051].
Regarding claims 12,13, Ding in view of Choi and Moreno discloses a semiconductor device, wherein the cavity has a depth in a range of 0.005 millimeters to 0.05 millimeters; wherein the recess has a depth in a range of 0.005 millimeters to 0.05 millimeters [Choi, 0007-0008].
Choi is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Ding. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Choi in the device of Ding because it will improve the electrical quality and reliability of the device [0051].
Regarding claim 14, Ding in view of Choi and Moreno discloses a semiconductor device, wherein the semiconductor chip is a transient voltage suppression device [0012].
Regarding claim 15, Ding in view of Choi and Moreno discloses a semiconductor device, wherein the clip (125, Ding) or (160, Choi) is L-shaped.
Claim(s) 8,16, is/are rejected under 35 U.S.C. 103 as being unpatentable over Ding in view of Choi and Moreno as applied to claims 1-7,9-15, and further in view of Yilmaz et al., (Yilmaz) US 2014/0361420.
Regarding claims 8,16, Ding in view of Choi and Moreno discloses a semiconductor device, a semiconductor device wherein the first end of the clip (125) includes first and second prongs (member is placed into a grid groove).
Ding in view of Choi and Moreno differs from the claimed invention because he does not explicitly disclose a device first and second notches formed in opposing edges of the second end of the second lead frame.
Yilmaz discloses [0027] first and second notches formed in opposing edges of the second end of the second lead frame [0027].
Yilmaz is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Ding in view of Choi and Moreno. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yilmaz in the device of Ding in view of Choi and Moreno because it will optimize the size of the device [0027].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,3-9,11-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MARC - ANTHONY ARMAND
Examiner
Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813