DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant's election with traverse of Species A (Figs. 1A-1B ; claims 1, 3-9, 12-13 and 19-20 ) in the reply filed on 3.11.2026 is acknowledged. The traversal is on the ground(s) that Figs. 2-6 are “variations or alternative embodiments of Species A” and the examiner “must explain why there would be a serious burden on the Examiner” . This is not found persuasive because said variations/alternative embodiments , as the applicant alleges, are drawn to semiconductor layouts with different and non-obvious arrangements of active and dummy regions ; this reasoning was included in the previous Office Action (OA) which the applicant did not address. Furthermore, the previous OA clearly explains the reasons for serious search/examination burden which were not addressed by the applicant. The requirement is still deemed proper and is therefore made FINAL. Claims 10-11 and 14-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 3.11.2026. Claim Objections Claim 12 is objected to because of the following informalities: the entire clause “ a first gate structure extending …” should be in a new line and indented. See MPEP 608.01(m) . Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 1, 3-9, 12-13 and 19-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 1 , the limitations to “a first active region”, “a first dummy active region” and “ a second dummy active ” along with their corresponding claimed features all cause the claim to fail to comply with the written description requirement because there is no correspondence between the claimed limitation s and the disclos ure ; said lack of correspondence fails to reasonably convey possession to one skilled in the relevant art . The limitations to “a first active region”, “a first dummy active region” and “ a second dummy active ” along with their corresponding claimed features are only found in the Abstract, [0007] and/or [0008] in ipsis verbis form but “ The written description requirement is not necessarily met when the claim language appears in ipsis verbis in the specification ” (MPEP 2163.03). Moreover, none of the drawings and related text describe “a first active region”, “a first dummy active region” and “ a second dummy active ” along with their corresponding claimed features with sufficient clarity to reasonably convey possession to one skilled in the relevant art. Namely, except for Abstract, [0007] and/or [0008], which are not sufficient to show possession per MPEP 2163.03, there is no correspondence between the disclosed embodiments and the claimed features which raises the question of possession and the examiner deems it necessary to issue the instant rejection. None of the dependent claims 3-9 address this deficiency and are rejected along with claim 1 . Regarding claim 1 2 , the limitations to “ a first active region, a dummy active region, and a second active region sequentially arranged over a substrate ” along with their corresponding claimed features all cause the claim to fail to comply with the written description requirement because there is no correspondence between the claimed limitations and the disclosure; said lack of correspondence fails to reasonably convey possession to one skilled in the relevant art. The limitations to “ a first active region, a dummy active region, and a second active region sequentially arranged over a substrate ” along with their corresponding claimed features are only found in the Abstract, [0007] and/or [0008] in ipsis verbis form but “ The written description requirement is not necessarily met when the claim language appears in ipsis verbis in the specification ” (MPEP 2163.03). Moreover, none of the drawings and related text describe “ a first active region, a dummy active region, and a second active region sequentially arranged over a substrate ” along with their corresponding claimed features with sufficient clarity to reasonably convey possession to one skilled in the relevant art. Namely, except for Abstract, [0007] and/or [0008], which are not sufficient to show possession per MPEP 2163.03, there is no correspondence between the disclosed embodiments and the claimed features which raises the question of possession and the examiner deems it necessary to issue the instant rejection. None of the dependent claims 19-20 address this deficiency and are rejected along with claim 12. Claims 1, 3-9, 12-13 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1 , the limitations to “a first active region”, “a first dummy active region” and “ a second dummy active ” along with their corresponding claimed features all cause the claim to be indefinite as there is a lack of correspondence between the claim and the specification which is the basis for indefiniteness per MPEP 2173.03 (“ A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty ”). The limitations to “a first active region”, “a first dummy active region” and “ a second dummy active ” along with their corresponding claimed features are only found in the Abstract, [0007] and/or [0008] in ipsis verbis form but none of the drawings and related text describe “a first active region”, “a first dummy active region” and “ a second dummy active ” along with their corresponding claimed features with sufficient clarity to determine the scope of the claim. Namely, except for Abstract, [0007] and/or [0008], which are not sufficient to show definiteness, there is no correspondence between the disclosed embodiments and the claimed features which creates a conflict/inconsistency between the claim and the specification which render the claim indefinite per MPEP 21703.03. None of the dependent claims 3-9 address this deficiency and are rejected along with claim 1. Regarding claim 1 2 , the limitations to “ a first active region, a dummy active region, and a second active region sequentially arranged over a substrate ” along with their corresponding claimed features all cause the claim to be indefinite as there is a lack of correspondence between the claim and the specification which is the basis for indefiniteness per MPEP 2173.03 (“ A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty ”). The limitations to “ a first active region, a dummy active region, and a second active region sequentially arranged over a substrate ” along with their corresponding claimed features are only found in the Abstract, [0007] and/or [0008] in ipsis verbis form but none of the drawings and related text describe “ a first active region, a dummy active region, and a second active region sequentially arranged over a substrate ” along with their corresponding claimed features with sufficient clarity to determine the scope of the claim. Namely, except for Abstract, [0007] and/or [0008], which are not sufficient to show definiteness, there is no correspondence between the disclosed embodiments and the claimed features which creates a conflict/inconsistency between the claim and the specification which render the claim indefinite per MPEP 21703.03. None of the dependent claims 19-20 address this deficiency and are rejected along with claim 12. Claim Rejections - 35 USC § 102 and 35 USC § 103 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 12 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kwon et al. ( US 20090121296 A1 ). Regarding claim 1 2 , Kwon discloses a semiconductor structure (Figs. 4-7) , comprising: a first active region (middle 21b) , a dummy active region (21c) , and a second active region (right 21b) sequentially arranged over a substrate (20) in a first direction (horizontal in Fig. 4) ; a first gate structure (24b) extending over the first active region (middle 21b) in a second direction (vertical in Fig. 4) , wherein the second direction is perpendicular to the first direction; a second gate structure (24b) extending over the second active region (right 21b) in the second direction; a first dummy gate structure (24c) extending over the dummy active region in the second direction (Fig. 4) , wherein (total) a length of the first dummy gate structure in the second direction is longer than a (total) length of the first dummy active region in the second direction (Fig. 4) ; and an isolation structure (22) surrounding the first active region, the dummy active region, and the second active region, the isolation structure comprising a portion located between the first active region (middle 21b) and the dummy active region (21c) , and the first dummy gate structure (24c) covering an upper surface of the portion of the isolation structure (Fig. 4; note that 24c extends laterally over 21c towards the middle 21b). Claim s 1 , 3 , 5-9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. ( US 20090121296 A1 ) in view of Moriwaki et al. ( US 20160027778 A1 ). Regarding claim 1 , Kwon discloses a semiconductor structure (Figs. 4-7), comprising: a first active region (middle 21b) disposed over a substrate (20), wherein the first active region has a first edge (vertical) extending in a first direction (vertical in Fig. 4), and a second edge (horizontal) connected to the first edge and extending in a second direction (horizontal in Fig. 4), wherein the first direction is perpendicular to the second direction; a first gate structure (24b) extending over the first active region (middle 21b) in the first direction (vertical in Fig. 4); a first dummy active region (left 21c) disposed over the substrate, wherein the first dummy active region has a first edge (vertical) extending in the first direction (vertical in Fig. 4) and immediately adjacent to the first edge (vertical) of the first active region (middle 21b); a second dummy active region disposed over the substrate, wherein the second dummy active region has a first edge extending in the second direction and immediately adjacent to the second edge of the first active region a first dummy gate structure (24c) extending over the first dummy active region (left 21c) in the first direction (vertical in Fig. 4), wherein a (total) length of the first dummy gate structure in the first direction is longer than a (total) length of the first dummy active region in the first direction (Fig. 4); and an isolation structure (22) surrounding the first active region, the first dummy active region, and the second dummy active region , the isolation structure comprising a portion located between the first active region (middle 21b) and the first dummy active region (left 21c), and the first dummy gate structure (24c) covering an upper surface of the portion of the isolation structure (Fig. 4; note that 24c extends laterally over 21c towards the middle 21b). Kw o n fails to disclose a second dummy active region disposed over the substrate, wherein the second dummy active region has a first edge extending in the second direction and immediately adjacent to the second edge of the first active regio n, and, an isolation structure surrounding the second dummy active region . Moriwaki discloses (Fig. 4-2) a second dummy active region (5A) disposed over the substrate (1) , wherein the second dummy active region has a first edge (horizontal) extending in the second direction (horizontal in Fig. 4-2) and immediately adjacent to the second edge (horizontal) of the first active regio n (3), and, an isolation structure (4) surrounding the second dummy active region ([0159] . See also Fig. 7 ). It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Moriwaki in Kwon and arrive at the claimed invention so as to suppress threshold voltage shift (Moriwaki, [0016] , [0038] ). Regarding claim 3 , Kwon /Moriwaki discloses t he semiconductor structure of claim 1, wherein the first dummy gate structure (24c) covers the first edge (vertical) of the first dummy active region (left 21c, Fig. 4; note that 24c extends laterally over 21c towards the middle 21b). Regarding claim 5 , Kwon /Moriwaki discloses t he semiconductor structure of claim 1, w herein the first dummy active region (left 21c) has a second edge (horizontal) connected to the first edge (vertical) of the first dummy active region and extending in the second direction, and the second edge (horizontal) of the first dummy active region is aligned with the second edge (horizontal) of the first active region (Fig. 4) . Regarding claim 6 , Kwon / Moriwaki discloses t he semiconductor structure of claim 1, wherein no dummy gate structure is disposed over the second dummy active region (5A/5D, Figs. 4-2 and 7) . Regarding claim 7 , Kwon / Moriwaki discloses t he semiconductor structure of claim 1, wherein the second dummy active region (5A/5D) has a second edge (vertical) connected to the first edge (horizontal) of the second dummy active region and extending in the first direction (vertical in Figs. 4-2 and 7) , and a size of the second edge (vertical) of the second dummy active region is smaller than a size of the first edge (horizontal) of the second dummy active region (Figs. 4-2 and 7) . Regarding claim 8 , Kwon / Moriwaki discloses t he semiconductor structure of claim 7, wherein the second edge (vertical) of the second dummy active region (5A) is aligned with the first edge (vertical) of the first active region (3, Fig. 4-2) . Regarding claim 9 , Kwon / Moriwaki discloses t he semiconductor structure of claim 1, further comprising: an interconnect structure (at least 8, Figs. 2, 8 and 9) disposed (Fig. 7) over the first active region (3) , the first gate structure (12/11) , the first dummy active region (one 5D) , and the second dummy active region (another 5D) , wherein the interconnect structure is electrically connected to the first active region (via 15) and the first gate structure (via 17) , and is electrically isolated from the first dummy active region and the second dummy active region (Fig. 7) . Regarding claim 1 9 , Kwon discloses t he semiconductor structure of claim 12, further comprising: an interlayer dielectric layer (26) covering the first active region, the dummy active region, the second active region, the first gate structure, and the second gate structure (Figs. 4 and 7 annotated above in the rejection of claim 12). Kwon fails to disclose a first contact plug and a second contact plug located in the interlayer dielectric layer and respectively disposed over the second active region and the second gate structure, wherein no contact plug is disposed over the dummy active region. Moriwaki discloses (Fig. 7 ) a first contact plug (15) and a second contact plug ( 17 ) located in the interlayer dielectric layer (8, Figs. 8-9) and respectively disposed over the second active region (3) and the second gate structure (12/11) , wherein no contact plug is disposed over the dummy active region (Fig. 7) . It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Moriwaki in Kwon and arrive at the claimed invention so as to suppress threshold voltage shift (Moriwaki, [0016], [0038]) while allowing for means to electrically address active devices. Claim 1 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. ( US 20090121296 A1 ) in view of Wang et al. ( US 20110156149 A1 ). Regarding claim 13 , Kwon fails to disclose t he semiconductor structure of claim 12, wherein a width of the first dummy gate structure in the first direction is smaller than a width of the first dummy active region in the first direction. Wang discloses wherein a width of the first dummy gate structure (119) in the first direction (D1) is smaller than a width of the first dummy active region (118) in the first direction (Fig. 1) . It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the relative size of Wang in Kwon and arrive at the claimed invention so as to “ provide a global uniform pattern density to enhance the CMP process and achieve a global planarizing surface after by the CMP process ” (Wang, [0022]) and/or because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. ( US 20090121296 A1 ). Regarding claim 20 , Kwon discloses t he semiconductor structure of claim 12, wherein (Figs. 4-7 annotated above in claim 12 rejection) the first active region (middle 21b) is separated from the second active region (right 21b) by a first distance (which passes over the dummy active region, Fig. 7) , the dummy active region (21c) is separated from the second active region (right 21b) by a second distance (they are adjacent to each other, Fig. 7), and a ratio of the second distance to the first distance is less than 1 (because the second distance is less than the first one). Kwon fails to disclose a ratio of the second distance to the first distance is less than 0.33. It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at a value within the claimed range in Kwon so as to minimize a level difference between a cell region and a peripheral region by “ optimizing dummy gate parts ” (Kwon, Abstract and [0027-0028] ) and/or as a matter as a matter of routine experimentation (MPEP 2144.05) Examiner Note No prior art is applied to claim 4 because the prior art of record fails to disclose or suggest “ a second dummy gate structure extending over the first dummy active region in the first direction, wherein a distance between the first dummy gate structure and the second dummy gate structure is longer than a distance between the first dummy gate structure and the first active region ”, however, the claim is not objected for including allowable subject matter in view of the 35 USC rejections above. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT ANDRES MUNOZ whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3346 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 8AM-5PM Central Time . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Eva Montalvo can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)270-3829 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Andres Munoz/ Primary Examiner, Art Unit 2818