DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Application 18/496,509 filed on 10/27/2023. Claims 1-20 are pending in the office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 1 recited the limitation “a layout element” unclear that the phase “element” refers to “a component” or “entire of an integrated circuit”. Also unclear the relationship between “element” to “component” or “an integrated circuit”.
Claims 11, 12, and 17 are also rejected as the similar above issue.
Claims 2-10, 13-16, and 18-20 are also rejected because are depended directly or indirectly from claims 1, 12, and 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-9, and 11-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al., (U.S. Pub. 2016/0132627).
As per claim 1: Tsai discloses a method (‘627, the abstract), comprising:
receiving an integrated circuit (IC) layout pattern that includes a shape corresponding to a component of the layout pattern (‘627, the abstract, receiving a layout of an integrated circuit (IC) device; fig. 1, 102, par. [0020] [0046], the circuit physical design the features of the circuit design are converted to a geometric representation of shapes, typically called a layout);
retrieving a mathematical definition of the shape from a shape database (‘627, fig. 6, par. [0027], the templated library (database) includes plurality of parameterized shape elements, also includes a mathematical description (definition) of the shape element, see fig. 7 and fig. 8, 804, par. [0028], mathematical relationship 804 defined variable that are later defined and selected);
receiving parameter inputs regarding characteristics of the shape (‘627, fig. 1, 106, par. [0026] [0027], the parameter are aspects that define the shape elements where a value of the description may be later defined or selected, fig. 6, parameterize selected shape type 604, and par. [0077], block 604 where one or more inputs defined the shape types are parameterized);
generating a vertex listing (i.e., pair of x and y coordination or position) (Examiner notes: specification [0059]) based on the mathematical definition of the shape and the parameter inputs (‘627, fig. 7, 704 and fig. 8, 804, par. [0027] [0028], vertical, horizontal, rotation positions, etc. or any point (x, y) within the shape); and
creating a layout element including the shape based on the vertex listing (‘627, fig. 7-10, par. [0025] [0027] [0038], OPC layout 218/mask 222).
As per claim 2: Tsai discloses the method of claim 1, further comprising converting the vertex listing to a graphics format (‘627, par. [0021] [0046], GDS file format).
As per claim 3: Tsai discloses the method of claim 2, wherein the graphics format includes a graphical data system file format (‘627, par. [0021] [0046], GDS file format).
As per claim 4: Tsai discloses the method of claim 1, wherein the mathematical definition includes a mathematical formula stored in the shapes database (‘327, fig. 6, 600 and also see fig. 7-8 include formula 804, par. [0027] and par. [0028]).
As per claim 5: Tsai discloses the method of claim 1, wherein the shape is a 2-dimensional (2D) shape (‘627, fig. 7, see the right hand side of table represent as 2D).
As per claim 7: Tsai discloses the method of claim 1, further comprising: receiving a manufacturing grid corresponding to the layout pattern (‘627, fig. 2, 206, fig. 4-5, par. [0061] [0063] [0067] included manufacturing grid); and wherein the vertex listing is generated further based on the manufacturing grid (‘629, fig. 9-10, parameter represents for manufacturing grid).
As per claim 8: Tsai discloses the method of claim 1, further comprising generating a photolithographic mask based on the layout element (‘672, OPC layout 218).
As per claim 9: Tsai discloses the method of claim 8, further comprising fabricating an IC based on the photolithographic mask (‘627, fig. 9-10, mask 222).
As per claim 11: Tsai discloses the method of claim 1, wherein the shape is a first shape (‘627, fig. 9, 902), the mathematical definition is a first mathematical definition and the vertex listing is a first vertex listing (‘627, fig. 7-9), wherein the received IC layout pattern includes a second shape (‘627, fig. 9, 906), and wherein the method further comprises: retrieving a second mathematical definition of the second shape from the shape database (‘627, fig. 6-9, similar to first shape as per claim 1); receiving further parameter inputs regarding characteristics of the second shape (‘627, fig. 7-9, similar to first shape as per claim 1); generating a second vertex listing based on the second mathematical definition of the second shape and the further parameter inputs (‘627, fig. 7-9, similar to first shape as per claim 1); and wherein the layout element is based on the first and second vertex listings (‘627, fig. 9, 218).
As per claim 12: Tsai discloses a system (‘627, fig. 3, 300), comprising:
a processor (‘627, fig. 3, 310);
a shape database accessible by the processor and storing a plurality of mathematical definitions of a plurality of shapes (‘627, fig. 3, 352, and fig. 6);
a memory storage accessible by the processor and storing instructions that when executed by the processor perform a method (‘627, fig. 3, 324) comprising:
receiving an integrated circuit (IC) layout pattern that includes a first shape corresponding to a first component of the layout pattern (‘627, the abstract, receiving a layout of an integrated circuit (IC) device; fig. 1, 102, par. [0020] [0046], the circuit physical design the features of the circuit design are converted to a geometric representation of shapes, typically called a layout);
retrieving a mathematical definition of the first shape from the shape database; receiving parameter inputs regarding characteristics of the first shape (‘627, fig. 6, par. [0027], the templated library (database) includes plurality of parameterized shape elements, also includes a mathematical description (definition) of the shape element, see fig. 7 and fig. 8, 804, par. [0028], mathematical relationship 804 defined variable that are later defined and selected);
generating a vertex listing (i.e., pair of x and y coordination or position) (Examiner notes: specification [0059]) based on the mathematical definition of the shape and the parameter inputs (‘627, fig. 7, 704 and fig. 8, 804, par. [0027] [0028], vertical, horizontal, rotation positions, etc. or any point (x, y) within the shape);
converting the vertex listing to a layout geometry format (‘627, fig. 9, transformation 914); and
creating a layout element including the first shape (‘627, fig. 7-10, par. [0025] [0027] [0038], OPC layout 218/mask 222).
As per claim 13: Tsai discloses the system of claim 12, wherein the IC layout pattern includes a passive component (i.e., capacitor plates) that includes the first shape (‘627, par. [0021] [0046], capacitor plates).
As per claim 14: Tsai discloses the system of claim 12, wherein the first shape represents a connector (i.e., gate feature, conductive lines) (‘627, par. [0021] [0046], gate feature, conductive lines).
As per claim 15: Tsai discloses the system of claim 12, wherein first shape represents a via (‘627, par. [0021] [0046], via).
As per claim 16: Tsai discloses the system of claim 12, wherein the plurality of mathematical definitions include mathematical formulas defining the plurality of shapes (‘627, fig. 8, 804).
As per claim 17: the method, comprising:
determining a plurality of mathematical definitions of a plurality of shapes (‘627, fig. 7-8);
storing the plurality of mathematical definitions in a shape database (‘627, fig. 3, 352, and fig. 6);
receiving an integrated circuit (IC) layout pattern by a processor, the IC layout including a first shape corresponding to a component of the layout pattern (‘627, the abstract, receiving a layout of an integrated circuit (IC) device; fig. 1, 102, par. [0020] [0046], the circuit physical design the features of the circuit design are converted to a geometric representation of shapes, typically called a layout);
retrieving a mathematical definition of the first shape from the shape database by the processor (‘627, fig. 6, par. [0027], the templated library (database) includes plurality of parameterized shape elements, also includes a mathematical description (definition) of the shape element, see fig. 7 and fig. 8, 804, par. [0028], mathematical relationship 804 defined variable that are later defined and selected);
receiving parameter inputs regarding characteristics of the first shape by the processor (‘627, fig. 1, 106, par. [0026] [0027], the parameter are aspects that define the shape elements where a value of the description may be later defined or selected, fig. 6, parameterize selected shape type 604, and par. [0077], block 604 where one or more inputs defined the shape types are parameterized);
creating a layout element including the first shape based on the mathematical definition and the parameter inputs (‘627, fig. 7-10, par. [0025] [0027] [0038], OPC layout 218/mask 222).
As per claim 18: the method of claim 17, further comprising generating a vertex listing (i.e., pair of x and y coordination or position) (Examiner notes: specification [0059]) based on the mathematical definition and the parameter inputs (‘627, fig. 7, 704 and fig. 8, 804, par. [0027] [0028], vertical, horizontal, rotation positions, etc. or any point (x, y) within the shape)
As per claim 19: the method of claim 17, wherein the shape is a 2 dimensional (2D) shape (‘627, fig. 7, see the right hand side of table represent as 2D).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 10, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al., (U.S. Pub. 2016/0132627).
As per claims 6 and 20: Tsai is silent the shape is a 3-dimensional (3D) shape.
However, Tsai teaches a main feature of layout can be “a VIA”.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention understood that “a Via” can represent 3-dimensional (3D) shape without doubt.
As per claim 10: Tsai teaches different shapes (i.e., classified shapes) such as polygons, rectangle, circle, ellipse, ring, pie, and/or arc (‘627, fig. 7, index 1-6). However, Tsai also teaches other shapes (unusual shapes) (‘627, fig. 7, index 7-8 for example).
Tsai does not teach if the shape database does not contain the mathematical definition of the shape, then creating the shape manually.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention can manually create “an unusual shape layout” by input any point within enclosed shape defined by connecting point with spline corresponding to the shape element parameters without undue experiment (In reVenner, 262 F.2d 91, 95, 120 USPQ 193, 194 (CCPA 1958) (The court held that broadly providing an automatic or mechanical means to replace a manual activity which accomplished the same result is not sufficient to distinguish over the prior art.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGHIA M DOAN whose telephone number is (571)272-5973. The examiner can normally be reached Mon - Fri 7:00 AM - 5:00 PM.
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/Primary Examiner, Art Unit 2851
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