DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statements filed on 9/03/2024 and 10/30/2023 have been acknowledged and signed copies of the PTO-1449 are attached herein.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-10, 13-18, and 20-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu et al. (US 2022/0013612 A1, hereinafter “Xu”).
In regards to claim 1, Xu discloses (See, for example, Figs. 2A, 4 and 7) a display device (See, Par [0144]) comprising:
a first conductive layer disposed on a substrate (10) and including a capacitor electrode (C2);
an active layer (41, C1, 31) disposed on the first conductive layer (C2) and including a switching active pattern (31, C1), the switching active pattern (31, C1) at least partially overlapping the capacitor electrode (C2) in a plan view and constituting a storage capacitor (Cst) together with the capacitor electrode (C2);
a second conductive layer (42, 22, 32) disposed on the active layer (41, C1, 31);
a pixel electrode layer (61) disposed on the second conductive layer (42, 22, 32) and including a pixel electrode,
the pixel electrode including:
a first part spaced apart from the switching active pattern in the plan view (the portion of the anode 61 in the light-emitting region AA that does not overlap C1 (i.e. the portion that is spatially separated from the entire switching active pattern, including its T1 channel region) reads on the limitation); and
a second part extending from the first part and overlapping the switching active pattern in the plan view (the portion of the anode 61 that does overlap C1, which is part of the same continuous active layer pattern as the switching active pattern of T1; See, for example, Par [0115]); and
a light emitting layer (62, See, for example, Par [0135]) disposed on the pixel electrode layer (61).
In regards to claim 15, Xu discloses (See, for example, Figs. 2A, 4 and 7) a display device comprising:
a first conductive layer (C2) disposed on a substrate (10) and including a capacitor electrode (See, Cst, Fig. 2A);
an active layer (41, C1, 21, 31) disposed on the first conductive layer (C2) and including:
a switching active pattern (31) at least partially overlapping the capacitor electrode (C2, See Cst in Fig. 2A) in a plan view and constituting a storage capacitor (Cst) together with the capacitor electrode; and
a driving active pattern (21) at least partially overlapping the capacitor electrode (See, Cst) in the plan view a second conductive layer (42, 22, 32) disposed on the active layer (41, C1, 21, 31) and including a gate electrode pattern at least partially overlapping the driving active pattern (21) in the plan view and constituting a driving transistor (T2) together with the driving active pattern (21);
a pixel electrode layer (61) disposed on the second conductive layer (42, 22, 32) and including a pixel electrode,
the pixel electrode including:
a first pixel electrode (See, for example, 61, P1, Figs. 4 and 7) disposed on the second conductive layer, electrically connected to the driving transistor (T2),
a part of the first pixel electrode overlapping the switching active pattern (31) in the plan view;
a second pixel electrode (See, for example, 61, P4, Figs. 4 and 7) spaced apart from the first pixel electrode (See, for example, 61, P1, Figs. 4 and 7); and
a third pixel electrode (See, for example, 61, P3, Figs. 4 and 7) spaced apart from the first (See, for example, 61, P1, Figs. 4 and 7) and second (See, for example, 61, P4, Figs. 4 and 7) pixel electrodes; and
a light emitting layer (62, See also Pars [0183]-0184]) disposed on the pixel electrode layer (61).
In regards to claim 2, Xu discloses (See, for example, Fig. 2A) wherein the second part of the pixel electrode overlaps an entirety of the storage capacitor in the plan view (“…the storage capacitor Cst is a transparent capacitor, and an orthographic projection of the storage capacitor Cst on the base substrate 10 coincides with the light-emitting region AA.”, See Par [0094]).
In regards to claim 3, Xu discloses (See, for example, Fig. 2A) wherein the active layer further includes: a driving active pattern (21) at least partially overlapping the capacitor electrode (C2) in the plan view; and
an initialization active pattern (41, although T3 is referred as a “sense transistor” rather than an “initialization transistor,” both perform the same structural and functional role of applying a reference voltage to the OLED anode through a third transistor active pattern) spaced apart from the driving active pattern (21) and the switching active pattern (31) in the plan view.
In regards to claim 4, Xu discloses (See, for example, Fig. 2B) wherein the second conductive layer (42, 22, 32) includes: a gate electrode (22) pattern at least partially overlapping the driving active pattern (21) in the plan view and constituting a driving transistor (T2) together with the driving active pattern (21); and a connection pattern (connection pattern in region A3) at least partially overlapping the capacitor electrode (C2) in the plan view and electrically connected to the driving active pattern (21) through contact holes (holes connecting 21 to C2 in region A3).
In regards to claims 6 and 20, Xu discloses (See, for example, Fig. 2A) wherein the gate electrode pattern (22) is electrically connected to the switching active pattern (31) through a contact hole (See the contact hole(s) connecting 22, 31 an dC1, Fig. 2A).
In regards to claim 7, Xu discloses (See, for example, Fig. 2A) wherein the second part of the pixel electrode (the portion of the anode 61 that does overlap C1, which is part of the same continuous active layer pattern as the switching active pattern of T1; See, for example, Par [0115]) is electrically connected to the connection pattern (connection pattern in region A3, See Fig. 2B) through a via hole (See, via hole, V2).
In regards to claim 8, Xu discloses (See, for example, Fig. 2A) a common electrode (63) disposed on the light emitting layer (62), wherein the pixel electrode (61), the light emitting layer (62), and the common electrode (63) constitute a light emitting element, and the light emitting element is electrically connected to the driving transistor (T2).
In regards to claim 9, Xu discloses (See, for example, Figs. 2A, 4 and 7) the light emitting element defines a sub-pixel (P1) that emits red light (R, See Par [0135]).
In regards to claim 10, Xu discloses (See, for example, Fig. 2A, See also claims 5 and 6) wherein the second conductive layer includes: a first scan line (G1) at least partially overlapping the switching active pattern (31) in the plan view and constituting a switching transistor (T1) together with a part of the switching active pattern (31); and a second scan line (G2) at least partially overlapping the initialization active pattern (41) in the plan view and constituting an initialization transistor (T3) together with a part of the initialization active pattern (41).
In regards to claim 13, Xu discloses (See, for example, Fig. 2A, and also Claim 8) wherein the first conductive layer further includes: a driving voltage line (VDD, Fig. 1, thru 24) extending in a second direction (Columns, See Par [0022]) and electrically connected (thru 24) to the driving active pattern (21); a data line (connected at 34; See also Fig. 1) extending in the second direction (Columns, See Par [0022]), spaced apart from the driving voltage line (VDD, Fig. 1, thru 24) in a first direction (data lines being in a column direction but spaced apart from the power lines. Hence, they can only be spaced apart in the Rows direction) intersecting the second direction (Columns), and electrically connected to the switching active pattern (31); and an initialization voltage line (Sense) extending in the second direction (Column, Par [0022]), spaced apart from the driving voltage line (VDD, Fig. 1, thru 24) in a direction opposite to the first direction, and electrically connected to the initialization active pattern (41).
In regards to claim 14, Xu discloses (see, for example, Fig. 2A) wherein the active layer includes a metal oxide semiconductor (See, for example, Par [0133]).
In regards to claim 16, Xu discloses (See, for example, Figs. 2A, 4 and 7) a part of the first pixel electrode overlaps an entirety of the storage capacitor in the plan view (“…the storage capacitor Cst is a transparent capacitor, and an orthographic projection of the storage capacitor Cst on the base substrate 10 coincides with the light-emitting region AA.”, See Par [0094]).
In regards to claim 17, Xu discloses (See, for example, Figs. 2A, 4 and 7) that wherein the second conductive layer (42, 22, 32) further includes a connection pattern (connection pattern in region A3) at least partially overlapping the capacitor electrode (C2) in the plan view and being electrically connected to the driving active pattern (21) through contact holes (holes connecting 21 to C2 in region A3).
In regards to claim 18, Xu discloses (See, for example, Fig. 2A, 4 and 7) wherein the part of the first pixel electrode (61, of subpixel P1) is electrically connected to the connection pattern (connection pattern in region A3) through a via hole holes (holes connecting 21 to C2 in region A3).
In regards to claim 21, Xu discloses (See, for example, Fig. 2A) a common electrode (63) disposed on the light emitting layer (62), wherein the first pixel electrode (61, for P1, See Figs. 4/7), the light emitting layer (62, See Par [0135]), and the common electrode (63) constitute a first light emitting element (See, Par [0135]), the second pixel electrode (61, for P4, See Figs. 4/7), the light emitting layer (62), and the common electrode (63) constitute a second light emitting element (See, Par [0135]), and the third pixel electrode (61, for P3, See Figs. 4/7), the light emitting layer (62), and the common electrode (63) constitute a third light emitting element (See, Par [0135]).
In regards to claim 22, Xu discloses (See, for example, Fig. 2A) wherein the first light emitting element (See Par [0135]) defines a first sub-pixel (P1) that emits red light (R, See Fig. 4 and Par [0135]), the second light emitting element defines a second sub-pixel (P4) that emits green light (G, See Fig. 4 and Par [0135]), and the third light emitting element defines a third sub-pixel (P3) that emits blue light (B, See Fig. 4 and Par [0135]).
In regards to claim 23, Xu discloses (See, for example, Fig. 2A) wherein the active layer further includes an initialization active pattern (41) spaced apart from the driving active pattern (21) and the switching active pattern (31) in the plan view.
In regards to claim 24, Xu discloses (See, for example, Figs. 2A, 4 and 7) wherein the second conductive layer further includes: a first scan line (G1)at least partially overlapping the switching active pattern (31) in the plan view and constituting a switching transistor (T1) together with a part of the switching active pattern (31); and a second scan line (G2) at least partially overlapping the initialization active pattern (41) in the plan view and constituting an initialization transistor (T3) together with a part of the initialization active pattern (41).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Nathan et al. (USPN 7248236 B2, hereinafter “Nathan”).
In regards to claims 5 and 19, Xu discloses all limitations of claim 4 and 15 above except that wherein the pixel electrode overlaps an entirety of the gate electrode pattern in the plan view.
Nathan while disclosing an OLED display teaches wherein the pixel electrode overlaps an entirety of the gate electrode pattern in the plan view (“an entire region between a source and drain of the at least one thin-film transistor”, Claim 1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Xu by Nathan because this would help minimizing parasitic capacitances to enhance the performance thereof.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Li et al. (US 2022/0028954 A1, hereinafter “Li”).
In regards to claim 11, Xu discloses (See, for example, Figs. 4 and 7) wherein the first scan line (G1) includes: a main part extending in a first direction (row direction); and a branch part (for example, gate electrode 32) from the main part in a second direction (in a column direction) intersecting the first direction (row direction), and the branch part of the first scan line (G1) at least partially overlaps the switching active pattern (31) in the plan view.
However, Xu is silent about the details of the gate line having a branch part protruding and extending in a different direction than the main part of the scan line.
Li while disclosing a display panel teaches (See, for example, Fig. 16) the gate line (GL1) having a branch part (64) protruding and extending in a different direction (in Y-direction, Par [0117]) than the main part (GL1, in the X-direction, Par [0116]) of the scan line.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Xu by Li because having to route the gate line signal across the pixel layout while extending a gate electrode portion to overlap the transistor’s active region to enable efficient signal distribution and TFT formation within a compact pixel.
In regards to claim 12, Xu discloses (See, for example, Figs. 4 and 7) The display device of claim 10, wherein the second scan line (G2) includes: a main part extending in a first direction (row direction); and a branch part (for example, gate electrode 32) from the main part in a second direction (column direction) intersecting the first direction (row direction), and the branch part of the second scan line (G2) at least partially overlaps the initialization active pattern (41).
However, Xu is silent about the details of the second gate line having a branch part protruding and extending from the main part in a second direction intersecting the first direction.
Li discloses (See, for example, Fig. 16) the second gate line (GL2) having a branch part (65) protruding and extending from the main part in a second direction (in Y-direction, Par [0117]) intersecting the first direction (GL2, in the X-direction, Par [0116]) of the scan line.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Xu by Li because having to route the gate line signal across the pixel layout while extending a gate electrode portion to overlap the transistor’s active region to enable efficient signal distribution and TFT formation within a compact pixel.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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