DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 6-11 have been cancelled; claim 1 has been amended; and claims 1-5 are currently pending.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2016/00278899 A1, hereinafter “Kim”) in view of Huang et al. (US 2012/0289040 A1, hereinafter “Huang”).
In regards to claim 1, Kim discloses (See, for example, Fig. 11-14) a method for fabricating a radio-frequency (RF) device, comprising:
providing a substrate (202) having a core region (204) and a non-core region (206);
forming a shallow trench isolation (STI) (208L, See annotated Fig. 13 included below) in the substrate (202) between the core region (204) and the non-core region (206);
removing (See, for example, Par [0069], Fig. 13) the first gate oxide layer (210) on the core region (204);
wherein after removing (See, for example, annotated Fig. 13 included below) the first gate oxide layer (210) on the core region (204), a part (Shown as 208c, See annotated Fig. 13 included below) of the shallow trench isolation (208L, See annotated Fig. 13 included below) is still covered by the first gate oxide layer (210), and another part (208e, See annotated Fig. 13 included below) of the shallow trench isolation (208L) is exposed.
Kim is silent about
forming a first gate oxide layer on the core region and the non-core region;
forming a patterned mask on the non-core region and the STI;
forming a second gate oxide layer on the core region.
Huang while disclosing a semiconductor structure teaches (See, for example, Figs. 2-)
forming a first gate oxide layer (203) on the core region (210) and the non-core region (220);
forming a patterned mask on the non-core region and the STI (See, for example, Par [0015], and Fig. 4);
removing (See, Par [0015] and Fig. 4) the first gate oxide layer (203) on the core region (210); and
forming a second gate oxide layer (204) on the core region (210).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Kim by Huang because having the method of Huang enhances device performance by improving the control over the surface roughness of the first dielectric layer in the non-core region by preventing damage of the first gate oxide layer in the non-core region during its removal from the core region.
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In regards to claim 2, Kim as modified above discloses (See, for example, Figs. 12-13, Kim)
removing (See, Fig. 13) the first gate oxide layer (210) on the core region (204, Fig. 13) and part of the first gate oxide layer (210, Fig. 13) on the STI (208, Fig. 13);
forming the second gate oxide layer (220/222, Fig. 14) on the core region (204); and
forming a gate material layer (270, 230, See Par [0072] and Fig. 15) on the first gate oxide layer (262) and the second gate oxide layer (220/222).
In regards to claim 3, Kim as modified above discloses (See, for example, Fig. 15, Kim) the gate material layer comprises polysilicon (See, for example, Par [0072]).
In regards to claim 4, Kim as modified above discloses (See, for example, Fig. 16) a thickness of the second gate oxide layer (220/222) is less than a thickness of the first gate oxide layer (262).
In regards to claim 5, Kim as modified above discloses (See, for example, Fig. 2, Huang) the substrate (201) comprises a silicon-on-insulator (SOI) substrate (See, for example, Par [0010]).
Response to Arguments
Applicant’s arguments with respect to the new amendment in claim 1 has been considered and are addressed in the rejection stated above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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