Prosecution Insights
Last updated: April 19, 2026
Application No. 18/497,089

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Oct 30, 2023
Examiner
WOLDEGEORGIS, ERMIAS T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
DENSO CORPORATION
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
3y 0m
To Grant
83%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allow Rate
526 granted / 743 resolved
+2.8% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
49 currently pending
Career history
792
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
68.7%
+28.7% vs TC avg
§102
26.6%
-13.4% vs TC avg
§112
3.6%
-36.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 743 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). Information Disclosure Statement The information disclosure statement filed on 10/30/023 has been acknowledged and a signed copy of the PTO-1449 is attached herein. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saito et al. (US 2012/0068357 A1, hereinafter “Saito”). In regards to claim 1, Saito discloses (See, for example, Fig. 10A/10B) a semiconductor device comprising: a lead frame (10); a semiconductor element (20P) mounted on the lead frame; a clip (40A) bonded through a bonding material (52) to an electrode (202, See, for example, Fig. 2B) on a surface of the semiconductor element (20P) opposite to the lead frame; a sealing material (60) covering the semiconductor element (20P) and the clip (40A); and an insulating layer (22) serving as a thermal resistance portion, the insulating layer (22) disposed in a bonding region (proximate to 52) bonded through the bonding material (52) between the semiconductor element (20P) and the clip (40A), wherein the insulating layer (22) is covered with (at least on one side) the bonding material (52), and has a thermal resistance higher than that of a different portion in the bonding region. In regards to claim 2, Saito discloses (See, for example, Figs. 10A/10B) in the bonding region, a single insulating layer (22) is disposed at a position separated from an outer contour of the electrode (202, See for example, Fig. 2B). Allowable Subject Matter Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 30, 2023
Application Filed
Dec 16, 2025
Non-Final Rejection — §102
Apr 01, 2026
Interview Requested
Apr 15, 2026
Applicant Interview (Telephonic)
Apr 15, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Apr 07, 2026
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2y 5m to grant Granted Mar 31, 2026
Patent 12588365
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2y 5m to grant Granted Mar 24, 2026
Patent 12588398
TOUCH DISPLAY PANEL AND PREPARATION METHOD THEREOF, AND DISPLAY APPARATUS
2y 5m to grant Granted Mar 24, 2026
Patent 12580019
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
83%
With Interview (+11.9%)
3y 0m
Median Time to Grant
Low
PTA Risk
Based on 743 resolved cases by this examiner. Grant probability derived from career allow rate.

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