DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 12-14 and 17-20 have been amended; and claims 1-20 are currently pending.
Election/Restrictions
Applicant’s election without traverse of invention Group I, claims 1-10, in the reply filed on 03/09/2026 is acknowledged. Claims 11, 15, and 16 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/09/2026.
Information Disclosure Statement
The information disclosure statements filed on 2/11/2025 and 8/14/2025 have been acknowledged and signed copies of the PTO-1449 are attached herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-10, 12-14, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2014/0035143 A1) in view of Chang et al. (US 2017/0053870 A1, hereinafter “Chang”).
In regards to claim 1, Lee discloses (See, for example, Fig. 4) a method of forming tapered vias between metal layers in semiconductor devices, the method comprising:
forming a first mask (326) over a substrate (302), wherein the first mask (326) comprises a first pattern (See, Fig. 9) for a first feature, and
the substrate comprises:
a first insulator layer (324);
a second insulator layer (322) under the first insulator layer (324); and
a metal layer (318) under the second insulator layer (306),
wherein the metal layer comprises a second feature (metal layer comprising a second feature);
removing a portion of the first insulator layer (See, Fig. 10) that is exposed through the first mask (326) to define the first feature in the second insulator layer (322);
forming a second mask (330) over the substrate (302), wherein the second mask (330) comprises a second pattern (See, Fig. 11) for a via that connects the first feature to the second feature (See, for example, Fig. 13); and
performing a directional etch (See, for example, Fig. 12) through the second mask (330) and the first insulator layer (324).
However, Lee fails to explicitly teach that the directional etch defines a recess for the via such that a first cross-sectional area of the via at the first feature is smaller than a second cross-sectional area at the second feature.
Chang while disclosing an interconnection structure teaches (See, for example, Figs. 4B and 10B; See also Pars [0060]-[0061]) the directional etch defines a recess (510/810) for the via such that a first cross-sectional area (515/815) of the via at the first feature is smaller than a second cross-sectional area at the second feature (516/816).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Lee by Chang because such geometry provides a larger overlay area between the via and the metal features, reduces via resistance, and increases critical dimension design budget during manufacturing.
In regards to claim 2, Lee as modified above discloses (See, for example, Figs. 9, 11 and 12) removing the first mask (See, Figs. 9 and 10, and Par [0032]) before forming the second mask (See, for example, Figs. 10 and 11), wherein an opening in the second pattern for the via overlaps with an opening in the first pattern for the first feature (See, 334 and 332, Fig. 12).
In regards to claim 3, Lee as modified above discloses (See, for example, Figs. 4B and 10B, Chang) the opening in the second pattern (725, Fig. 9B) for the via is larger than the opening in the first pattern for the first feature (726, See. Fig. 9B).
In regards to claim 4, Lee as modified above discloses the directional etch comprises a directional reactive-ion etch (RIE), and an angle of the directional RIE defines a taper of the recess for the via (“the DA plasma etch process is controlled such that the etching bias along the first direction A-A is greater than the etching bias along the second direction B-B. In one embodiment, the etching bias along the first direction A-A is a positive etching bias while the etching bias along the second direction B-B is a negative etching bias.”, See, Chang, Pars [0058]-[0060]).
In regards to claim 5, Lee as modified above discloses (See, for example, Fig. 14) forming a first liner (336) in the recess for the via (332); forming a second liner (338) over the first liner (336) in the recess for the via (332); and filling the recess for the via with a conductive fill material inside the second liner (“… filling the via 332 and the second trench 334 as shown in FIG. 13…”, See, for example, Par [0035], and Par [0036]).
In regards to claim 9, Lee as modified above discloses (See, for example, Fig. 14) the first insulator layer (322) forms a first metal layer (340) when the first feature is formed in the first insulator layer (322).
In regards to claim 10, Lee as modified by Chang discloses (See, for example, Fig. 6D, and 10B, Chang) the first feature comprises a first conductive wire in a first metal layer (215, along first direction A-A), the second feature comprises a second conductive wire (620 or 820, along the second direction B-B) in the metal layer, and the first conductive wire (215) runs in a direction that is orthogonal (A-A is perpendicular to B-B) to the second conductive wire (620/820).
In regards to claim 12, Lee as modified above discloses (See, for example, Figs. 4B, 4F, 6D, and 10B, Chang) the first cross-sectional area comprises a width equal to a width of the first feature, and a length equal to a width of the second feature (the top surface 515/815 of the via has its shorter dimension (L3) along the first direction A-A (See, Pars [0056], and [0060]-[0061]). The top surface dimension along the second direction B-B matches the direction of the lower metal line 215 corresponding to the width of the second feature. The top surface dimension along the first direction A-A corresponds to the width of the first feature (upper metal line). Combining with Lee’s via 332 connecting the second trench 334 to the first trench metal 318 (See, Pars [0038]-[0039]), the combination renders obvious a first cross-sectional area having a width equal to the first feature an a length equal to the second feature width).
In regards to claim 13, Lee as modified above discloses (See, for example, Figs. 4B, 4F, 6D, and 10B, Chang) the second cross-sectional area comprises a width equal to a width of the second feature, and a length that is greater than a width of the first feature (the bottom surface 516/816 of the via has a fifth length (L5) along the first direction A-A that is longer than the third length L3 of the top surface (See, Par [0060]). The bottom surface is elongated along the same direction as the lower metal line (215, Pars [0060] and [0072]). Thus, the second cross-sectional area at the bottom has a width equal to the width of the second feature (lower metal line) and length (L5) that is greater than the width of the first feature (upper metal line, which has its shorter dimension along the first direction)).
In regards to claim 14, Lee as modified above discloses (See, for example, Figs. 4B, 4F, 6D, 10B, Chang) the via continuously tapers to become larger in a direction parallel to the second feature as the via extends from the first cross-sectional area to the second cross-sectional area (a dimension of the via along the first direction (parallel to the lower metal line/second feature) continuously increases as the height of the via increases from the top surface to the bottom surface (See, for example, Claim 29, Pars [0060] and [0074]). The via continuously tapers to become larger in the direction parallel to the second feature as the via extends from the first cross-sectional area (top) to the second cross-sectional area (bottom)).
In regards to claim 18, Lee as modified above discloses all limitations of claim 1 except that a resistance of the via is between about 13.5 ohms and about 23 ohms.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have a resistance of the via is between about 13.5 ohms and about 23 ohms because this is a property that flows naturally from the structural configuration of the tapered via. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977); See also MPEP 2112.01(I).
In regards to claim 19, Lee as modified above discloses (See Par [0067], Chang) that a resistance of the via is reduced (the tapered via geometry provides a larger overlay and reduces via resistance compared to a conventional (non-tapered) via).
However, Lee as modified by Chang further fails to explicitly teach a via resistance reduction by between about 25% and about 45% in comparison to a second via that does not taper between the first feature and the second feature.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have a via resistance reduction by between about 25% and about 45% in comparison to a second via that does not taper between the first feature and the second feature, since the combination teaches a tapered via with the same structural configuration as the claimed invention (expanding from the first feature to the second feature with a controllable taper angle and desired liner materials), the resistance reduction would inherently result from the taught structure. See In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977); See also MPEP 2112.01(I). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to optimizing the taper angle to achieve the claimed resistance range, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claims 6-8, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chang as applied to claim 1 above, and further in view of Hwang et al. (KR 20210110782 A, hereinafter “Hwang”).
In regards to claim 6, Lee as modified above discloses all limitations of claim 1 and the first liner (336), a second liner (338), and a conductive fill material comprises copper (340, See Par [0036]).
However, Lee as modified by Chang fails to teach that the first liner comprises titanium nitride; and the second liner comprises cobalt.
Hwang while disclosing method of manufacturing semiconductor device teaches (see, for example, Fig. 1) the first liner (122) comprises titanium nitride 9See, page 2-3); and the second liner (124) comprises cobalt (See, page 3).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Lee further with Hwang because the liner materials of Hwang help reduce electromigration by suppressing diffusion of the copper fill material.
In regards to claim 7, Lee as modified above discloses all limitations of claim 1 except that wherein the directional etch is selective to the second insulator layer relative to the first insulator layer, such that the directional etch etches the second insulator layer faster than the first insulator layer.
Hwang discloses (See, for example, Figs. 4 and 5) the directional etch is selective to the second insulator layer relative to the first insulator layer, such that the directional etch etches the second insulator layer faster than the first insulator layer (an etch stop layer 140 between the first insulator layer 110 and the second insulator layer 150, wherein the etching process for forming a via hole OP2a proceeds through the second insulator layer 150 and stops at the etch stop layer 140. (See, pp. 6-7). The first region D1 (See Fig. 4) of the etch stop layer 140 in which impurities are present has higher etch resistance than the second region D2 (See, page 6). Therefore, the via etching through the second insulating layer proceeds at a faster rate than through the etch stop layer and the first insulating layer, demonstrated etch selectivity between insulating layers.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Lee further with Hwang because this would help achieve precise control over sidewall profiles and critical dimensions, and preserve the integrity of adjacent layers during pattern transfer.
In regards to claim 8, Lee as modified above discloses all limitations of claim 1 except that the substrate further comprises an etch stop layer between the first insulator layer and the second insulator layer, and removing the portion of the first insulator layer comprises etching the first insulator layer that is exposed through the first mask until the etch stop layer is exposed.
Hwang discloses (See, for example, Fig. 13) the substrate further comprises an etch stop layer (140) between the first insulator layer (150) and the second insulator layer (110), and removing the portion of the first insulator layer (See, Fig. 13, 150) comprises etching the first insulator layer (150, See also. Page 7) that is exposed through the first mask until the etch stop layer (140) is exposed (See, page 7, “a photo and an etching process on the … insulator layer 150.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Lee further with Hwang because this would help control etch depth, prevent over-etching into underlying layers, and protect the integrity of underlying structures during the etching process.
In regards to claim 17, Lee as modified above discloses (See, for example, Figs. 4B, $F, 6D, and 10B, Chang) wherein the via tapers outwards from the first feature at an angle of between about 10° and about 35° (the DA plasma etch process directs a plasm a flux at angle of incidence θ with respect to a normal line of the surface, and the angle of incidence θ changes in a range of about zero degrees to less than 90 degrees (See, Par [0058]). During the DA plasma etch, the angle of incidence θ is controlled to change in a dynamic mode and results in a varying etch bias from one direction to another. The purpose of the DA plasm etch is to provide a larger overlay and reduce via resistance (See, Par [0067]). Thus, Chang establishes the tech angel as a result effective variable that directly controls the via profile, which in turn directly affects the overlay area, alignment tolerance, and resistance of the via).
However, Lee as modified above further fails to explicitly teach that a titanium nitride liner and a cobalt liner surrounding a copper fill material in the via.
Hwang teaches (see, for example, Fig. 1) the first liner (122) comprises titanium nitride 9See, page 2-3); and the second liner (124) comprises cobalt (See, page 3) surrounding a copper fill material (126) in the via (See, for example, OP1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Lee further with Hwang because the liner materials of Hwang help reduce electromigration by suppressing diffusion of the copper fill material.
In regards to claim 20, Lee as modified above discloses (See, for example, Figs. 8 and 9A-9C, Chang) a length of the via along the first feature is equal to a width of the second feature plus twice the height of the via multiplied by a tangent of the angle (a via sidewalls have s sidewall profile 727 which may include a straight-line profile (See, Par [0071]). For any via having a linear taper at an angle θ from vertical with a height H_via, the geometric relationship dictates that the length of the via at the bottom equals the top dimension plus twice the height multiplied by the tangent of the angle (i.e. L = W_top + 2*H_via*tan(θ)). This is basic trigonometric identity describing the geometry of any linearly tapered structure).
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
Prosecution Insights