DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention III which corresponds to claims 17-20 in the reply filed on 5/18/2026 is acknowledged. Claims 1-16 are withdrawn from further consideration, pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Inventions or Species. New claims 21-36 are added.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Methods for Fabricating Integrated Circuit Interconnect Structures with Misaligned Metal Vias and Overlying Metal Lines.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17-18 and 21 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yang et.al. (US-20210375749A1, hereinafter Yang)
Regarding Claim 17.
Yang teaches in Fig.2 and in related text A method for fabricating an integrated circuit device (#200), comprising: forming a first metallization layer (#115) over a substrate (#102), wherein the first metallization layer comprises two adjacent first metal lines (#115a and #115b); forming a second metallization layer (#126) over the first metallization layer, wherein forming the second metallization layer comprises: depositing a dielectric layer (#218 & #120) over the first metallization layer (#115); etching a trench opening (#116) and a via opening (#122) communicated with the trench opening in the dielectric layer, wherein the via opening is between the first metal lines (#232 is between #115a and #115b) and misaligned with the first metal lines in a top view; and depositing a conductive material into the trench opening and the via opening. ([0018-0028])
Regarding Claim 18.
Yang teaches The method of claim 17,
Yang further teaches in Fig.2 and in related text wherein etching the via opening is performed such that a bottom of the via opening is laterally aligned with the first metal lines. (bottom of via #122 is aligned with layer #115) ([0018-0028])
Regarding Claim 21.
Yang teaches in Fig.2 and in related text A method for fabricating an integrated circuit device (#200), comprising: forming a transistor (#104) over a substrate (#102); and forming an interconnect structure (#150) over the transistor, wherein forming the interconnect structure comprises: forming a first metal line (#115a); forming a first metal via (#122) having a bottom surface (#232) below a top surface of the first metal line (#115a); and forming a second metal line (#126) over the first metal line and the first metal via, wherein the first metal via (#122) is connected with a bottom of the second metal line (#126). ([0018-0028])
Claims 29, 30 and 33-35 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Singh et.al. (US-20240186367A1, hereinafter Singh)
Regarding Claim 29.
Singh teaches in Fig.2C, 2H and 2I and in related text A method for fabricating an integrated circuit device, comprising: depositing a first dielectric layer (#209) over a substrate (#201); forming a first metal line (#227a/#227b) in the first dielectric layer; depositing a second dielectric layer (#213 +#211) over the first metal line; forming a first metal via (Fig. 2H #219) extending from the second dielectric layer (#213/#211) into the first dielectric layer (#209) and spaced apart from the first metal line (#227) through the first dielectric layer; and forming a second metal line (Fig.2I #221) over the first metal via (#219) and in the second dielectric layer (#213/#211). ([0081-0088])
Regarding Claim 30.
Singh teaches The method of claim 29,
Singh further teaches wherein a bottom surface of the first metal via (#219) is lower than a bottom surface of the first metal line (#227). ( As shown in FIGS. 2H and 2I, a distance (d) between the second metal surface of the unlanded via 219 and the first metal surface of the patterned metal 203 is determined by the depth of etch for the unlanded via 219 into the middle layer 209. As described above with reference to FIG. 2H, the distance (d) may be, e.g., 10-50 nm, determined by the amount of dielectric material remaining in the middle layer 209 after etching. Meaning the via descends nearly the full depth of the layer than houses #227a/#227b.) ([0081-0088])
Regarding Claim 33.
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Singh teaches The method of claim 29,
Singh further teaches in Fig. 2G further comprising forming a second metal via (as annotated) extending into the second dielectric layer (#213) and spaced apart from the second metal line (Fig.2I #221) through the second dielectric layer (#213).
Regarding Claim 34.
Singh teaches The method of claim 33,
Singh further teaches in Fig. 2G & 2I wherein a bottom surface of the second metal via (as annotated) is lower than a top surface of the second metal line (Fig.2I #221).
Regarding Claim 35.
Singh teaches he method of claim 33,
Singh further teaches in Fig. 2G wherein the second metal via (as annotated) is aligned with the first metal line (Fig.2C #227b) in the top view.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et.al. (US-20210375749A1, hereinafter Yang), and further in view of Edelstein et.al. (US-20190157201A1, hereinafter Edelstein)
Regarding Claim 19.
Yang teaches The method of claim 17,
Edelstein teaches in Fig.2 wherein etching the trench opening (#107a/#107b) is performed such that the trench opening extends along an extension direction of the first metal lines (#104/#105).
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Yang with the teachings of Edelstein, as identified above, in order to provide flexible/optimized routing between successive wiring levels while retaining Yang’s via and metallization process.
Regarding Claim 20.
Yang teaches The method of claim 17,
Edelstein teaches in Fig.5 wherein etching the via opening is performed such that the trench opening (Fig.5 #214) extends across an extension direction of the first metal lines (#104/#105). ([0040-0046] Edelstein teaches adjacent lower metal lines #104 and #105, and upper dielectric #110, and upper trench pattern #214 running perpendicular to and overlapping the lower metal lines, via patterns/openings communicating with the upper trenches; and dual-damascene formation of upper lines #118/#120 and vias)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Yang with the teachings of Edelstein, as identified above, in order to provide flexible/optimized routing between successive wiring levels while retaining Yang’s via and metallization process.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et.al. (US-20210375749A1, hereinafter Yang), and further in view of Booth et.al. (US- 20110049674A1, hereinafter Booth)
Regarding Claim 22.
Yang teaches The method of claim 21,
Booth teaches in Fig.2D and in related text wherein forming the interconnect structure further comprises: forming a third metal line at a same level as the first metal line, wherein the third metal line is electrically connected with the transistor; forming a second metal via over the third metal line and connected to the third metal line; and forming a fourth metal line at a same level as the second metal line and over the second metal via, wherein the fourth metal line is connected to the third metal line through the second metal via. (Booth Fig.2D, interconnect line #420/#440 and vias #422/#442 formed concurrently at the same levels, resistively connected to a semiconductor device Fig.2D. 3A-3B [0064-0065])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Yang with the teachings of Booth, because such structures are formed in the same processing steps used to form other metal interconnect structures, they may be manufactured without incurring an additional processing cost. Applying those steps also yields predictable results.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et.al. (US-20210375749A1, hereinafter Yang) in view of Booth et.al. (US- 20110049674A1, hereinafter Booth), and further in view of Mignot et.al. (US-20200388567-A1, hereinafter Mignot)
Regarding Claim 23
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Yang modified by Booth teaches The method of claim 22,
Mignot teaches in Fig.13 wherein a height of the first metal via (as annotated) is greater than a height of the second metal via (as annotated).
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Yang and Booth with the teachings of Mignot, as identified above, in order to have greater process-control flexibility over the height/dimension of metal and via layers, routing layout, and conductivity/resistance value of the device.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et.al. (US-20210375749A1, hereinafter Yang), and further in view of Okamoto et.al. (US-20140252653A1, hereinafter Okamoto)
Regarding Claim 26.
Yang teaches The method of claim 21,
Okamoto teaches in Fig.1 further comprising: forming a dummy transistor (#126 off transistor) over the substrate and below the interconnect structure (#118-#121), wherein the dummy transistor is vertically below the first metal via (#116). ([0077-0083])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Yang with the teachings of Okamoto, as identified above, in order to improve pattern-density uniformity and use available layout area.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et.al. (US-20210375749A1, hereinafter Yang), and further in view of Karpov et.al. (US-20240170394A1, hereinafter Karpov)
Regarding Claim 27
Yang teaches The method of claim 21,
Karpov teaches in Fig.8 further comprising: forming a dielectric layer (#826) surrounding the transistor (#801 transistor structures), wherein the bottom surface of the first metal via (#825 via) is in contact with the dielectric layer.
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Yang with the teachings of Karpov, as identified above, in order to ;provide better insulation and to improve pattern-density uniformity and use available layout area.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et.al. (US-20210375749A1, hereinafter Yang), and further in view of Chang et.al. (US- 20230205966-A1, hereinafter Chang)
Regarding Claim 28.
Yang teaches The method of claim 21,
Chang teaches in Fig.3B wherein a height of the second metal line (#H32) is greater than a height of the first metal line (#H31). ([0068])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Yang with the teachings of Chang, as identified above, as taller upper-level conductors reduce resistance for appropriate routing nets while the shorter lower level ones preserve routing density.
Claims 31-32 are rejected under 35 U.S.C. 103 as being unpatentable over Singh et.al. (US-20240186367A1, hereinafter Singh), and further in view of Booth et.al. (US-20110049674A1, hereinafter Booth)
Regarding Claim 31.
Singh teaches The method of claim 29,
Booth teaches in Fig.1A & 1B, Fig.5 wherein the second metal line (#10/#50) is formed such that the second metal line (#20/#60) is interlaced with the first metal line in a top view. ([0022][0073-0079])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Singh with the teachings of Booth, as identified above, in order to increase inter-layer capacitive coupling between the capacitor electrodes.
Regarding Claim 32
Singh teaches The method of claim 29,
Booth teaches in Fig.2A-2D, 3A-3B) wherein the second metal line (#10 in one layer) is formed such that the second metal line (#10 in another vertically adjacent layer) extends across the first metal line in a top view. ([0047-0065])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Singh with the teachings of Booth, as identified above, in order to increase inter-layer capacitive coupling between the capacitor electrodes.
Allowable Subject Matter
Claims 24-25 and 36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 24 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the method, wherein the bottom surface of the first metal via is below a level at three-quarter height of the first metal line.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 25 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the method, wherein a space between the first metal via and the first metal line is in a range from about 16 nanometers to about 32 nanometers. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 36 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the method, wherein an extension direction of the second metal via is different from an extension direction of the first metal via. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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