Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on May 12, 2026, regarding the application filed October 30, 2023.
Election/Restrictions
Applicant’s election without traverse of Invention I, corresponding to claims 1-11, in the reply filed on May 12, 2026 is acknowledged. Claim 12 has been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. This restriction requirement has been finalized.
Claims 1-12 are pending, with claim 12 currently withdrawn from consideration.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 25, 2025 has been placed in the application file and is being considered by the examiner.
Drawings
The drawings filed with the application on October 30, 2023 are accepted.
Claim Objections
Claims 1 and claims 2-11 dependent therefrom are objected to because of the following informalities: claim 1 recites, inter alia, “the die contact of the second type of first integrate circuit die” and “the die contact of the second type of second integrate circuit die”. This appears to be a typo and has been interpreted as: “the die contact of the second type of the first integrated the second integrated . Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noori et al., US 2021/0313293 A1 (hereinafter Noori).
Regarding claim 1, Noori discloses: A package configured to perform a function, the package comprising: a first integrated circuit die (Noori, FIG. 2A, 3D, die 210, [0092]) having a die contact of a first type (Noori, FIG. 2A, gate terminal 222, [0092]) and a die contact of a second type (Noori, FIG. 2A, drain terminal 224, [0092]), the die contact of the first type of the first integrated circuit die and the die contact of the second type of the first integrated (Noori, FIG. 2A, gate terminal 222, drain terminal 224, [0092]) each electrically connected to a first integrated circuit contained within the first integrated circuit die (Noori, FIG. 2A, 2B, gate terminal 222 [the die contact of the first type] and drain terminal 224 [the die contact of the second type] each connected to one of unit cell transistors 216 [the first integrated circuit] contained within die 210 [the first integrated circuit die], [0092; 0102; 0105]), the first integrated circuit structured to perform the function (Noori, one of unit cell transistors 216 [the first integrated circuit] is part of an RF transistor amplifier [the first integrated circuit structured to perform the function], [0092; 0106-0107]; );
a second integrated circuit die (Noori, FIG. 2A, 3D, second instance of die 210, [0092; 0150]) having a die contact of the first type (Noori, FIG. 2A, gate terminal 222, [0092]) and a die contact of the second type (Noori, FIG. 2A, drain terminal 224, [0092]), the die contact of the first type of the second integrated circuit die and the die contact of the second type of the second integrated (Noori, FIG. 2A, gate terminal 222, drain terminal 224, [0092]) each electrically connected to a second integrated circuit contained within the second integrated circuit die (Noori, FIG. 2A, 2B, 3D, gate terminal 222 [the die contact of the first type] and drain terminal 224 [the die contact of the second type] each connected to additional one of unit cell transistors 216 [the second integrated circuit] contained within die 210 [the second integrated circuit die], [0092; 0102; 0105; 0150]), the second integrated circuit structured to perform the function (Noori, additional one of unit cell transistors 216 [the second integrated circuit] is contained within RF transistor amplifier die 210 [the second integrated circuit structured to perform the function], [0150]);
a package contact of the first type (Noori, FIG. 2A, gate connection pad 272, [0094]);
a package contact of the second type (Noori, FIG. 2A, drain connection pad 274, [0094]);
a first common coupler that electrically connects the die contact of the first type of the first integrated circuit die and the die contact of the first type of the second integrated circuit die to the package contact of the first type (Noori, FIGs. 2A, 3D, conductive patterns 273 in the coupling element 270; “gate connection pad 272 [the package contact of the first type] may be electrically coupled to the gate terminal 222 [the die contact of the first type] by one or more conductive patterns 273 [the first common coupler] in the coupling element 270,” [0094]; “a single coupling element 270 may be coupled to a plurality of RF transistor amplifier dies 210,” [0147]); and
a second common coupler that electrically connects the die contact of the second type of the first integrated circuit die and the die contact of the second type of the second integrated circuit die to the package contact of the second type (Noori, FIGs. 2A, 3D, “drain connection pad 274 [the package contact of the second type] may be electrically coupled to the drain terminal 224 [the die contact of the second type] by one or more conductive patterns 273 [the second common coupler] in the coupling element 270,” [0094]; “The top side contacts may allow a coupling element [the common coupler] to be coupled directly to the gate, drain, and source terminals [the die contacts] of the RF transistor amplifier dies [the integrated circuit dies],” [0073]; “a single coupling element 270 may be coupled to a plurality of RF transistor amplifier dies 210,” [0147; 0093]).
Regarding claim 2, Noori discloses: The package according to Claim 1, the package further comprising: a package contact of a third type (Noori, FIG. 2A, source connection pad 276, [0094]); and a third common coupler (Noori, “source connection pad 276 [the package contact of the third type] may be electrically coupled to source terminal(s) 226 by one or more conductive patterns 273 [the third common coupler] in the coupling element 270,” [0094]); the first integrated circuit die further having a die contact of the third type (Noori, FIG. 2A, source terminal 226, [0092]) that is electrically connected to the first integrated circuit contained within the first integrated circuit die (Noori, FIG. 2A, 2B, source terminal 226 [the die contact of the third type] connected to one of unit cell transistors 216 [the first integrated circuit] contained within die 210 [the first integrated circuit die], [0092; 0102; 0105]); the second integrated circuit die (Noori, FIG. 2A, 3D, second instance of die 210, [0092; 0150]) further having a die contact of the third type (Noori, FIG. 2A, source terminal 226, [0092]) that is electrically connected to the second integrated circuit contained within the second integrated circuit die (Noori, FIG. 2A, 2B, 3D, source terminal 226 [the die contact of the third type] connected to additional one of unit cell transistors 216 [the second integrated circuit] contained within die 210 [the second integrated circuit die], [0092; 0102; 0105; 0150]); the third common coupler electrically connecting the die contact of the third type of the first integrated circuit die and the die contact of the third type of the second integrated circuit die to the package contact of the third type (Noori, FIGs. 2A, 3D, “source connection pad 276 [the package contact of the third type] may be electrically coupled to source terminal(s) 226 [the die contacts of the third type] by one or more conductive patterns 273 [the third common coupler] in the coupling element 270,” [0094]; “The top side contacts may allow a coupling element [the common coupler] to be coupled directly to the gate, drain, and source terminals [the die contacts] of the RF transistor amplifier dies [the integrated circuit dies],” [0073]; “a single coupling element 270 may be coupled to a plurality of RF transistor amplifier dies 210,” [0147; 0093]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Noori as applied to claim 1 above, and further in view of Klowak et al., US 2016/0240471 A1 (hereinafter Klowak).
Regarding claim 3, Noori teaches nearly every element of claim 3 but is silent regarding: a package contact of a fourth type; and a fourth common coupler; the first integrated circuit die further having a die contact of the fourth type that is electrically connected to the first integrated circuit contained within the first integrated circuit die; the second integrated circuit die further having a die contact of the fourth type that is electrically connected to the second integrated circuit contained within the second integrated circuit die; the fourth common coupler electrically connecting the die contact of the fourth type of the first integrated circuit die and the die contact of the fourth type of the second integrated circuit die to the package contact of the fourth type.
However, Klowak, in the same field of endeavor, teaches a GaN power transistor that includes a source, drain, and gate contact areas on a GaN die, analogous to the claimed die contacts of the first, second, third, and fourth types, each connected to respective external contact pads, analogous to the claimed package contacts, (Klowak, [0022; 0067; 0088]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Noori with the teachings of Klowak, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Klowak, to provide corresponding source, drain, gate and source sense contact areas for electrical connections (Klowak, [0086]), thereby providing for additional device functionality.
Claims 4 and 5 recite, inter alia, additional integrated circuit dies having integrated circuits structured to perform the function, as recited in claim 1, with respective die contacts connected to respective package contacts by respective common couplers.
Although Noori in view of Klowak does not explicitly teach a third integrated circuit die and a fourth integrated circuit die, and respective die contacts connected to respective package contacts by respective common couplers, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include additional integrated circuit die within the package because, as explicitly recognized by Klowak, it was known in the art to embed multiple chips together within a package (Klowak, [0037]), and Noori explicitly recognizes the advantages of using multiple transistor unit cells connected in parallel to improve current handling capabilities (Noori, [0007; 0102]). Therefore, it would have been obvious to a person having ordinary skill in the art to include additional integrated circuit dies and respective die contacts connected to respective package contacts by respective common couplers, because a person having ordinary skill would have recognized that applying the known techniques of Noori in view of Klowak would have yielded predictable results and resulted in improved current handling capabilities.
Furthermore, it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP 2144.04(VI)(B)).
Regarding claim 6, Noori in view of Klowak teaches: The package according to Claim 3, the first integrated circuit die and the second integrated circuit die together forming an integrated circuit die layer (Noori, FIG. 3D shows the integrated circuit die layer as the lowest layer, including RF transistor amplifiers 200), the package contacts of the first type, the second type, the third type and the fourth type each forming a package contact layer (Noori, FIG. 3D shows the package contact layer as the top layer, including surface connection pads 377), the first common coupler, the second common coupler, the third common coupler, and the fourth common coupler being between the integrated circuit die layer and the package contact layer (Noori, FIG. 3D shows the common coupler layer as the middle layer, including conductive patterns 373).
Claims 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Noori in view of Klowak, as applied to claim 3 above, and further in view of Hosokawa, U.S. Pat. No. 5,903,422 (hereinafter Hosokawa).
Regarding claim 7, Noori in view of Klowak teaches nearly every element of claim 7 but is silent regarding: the first integrated circuit comprising a first power field-effect transistor and a first sense field-effect transistor, and the second integrated circuit comprising a second power field-effect transistor and a second sense field-effect transistor.
However, Hosokawa, in the same field of endeavor, teaches: the first integrated circuit comprising a first power field-effect transistor (Hosokawa, FIG. 3, power MOS transistor 2; col. 4, lines 1-6) and a first sense field-effect transistor (Hosokawa, FIG. 3, sensing MOS transistor 3; col. 4, lines 7-15)
Hosokawa is silent regarding: the second integrated circuit comprising a second power field-effect transistor and a second sense field-effect transistor.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include the second integrated circuit comprising a second power field-effect transistor and a second sense field-effect transistor within the package because, as explicitly recognized by Klowak, it was known in the art to embed multiple chips together within a package (Klowak, [0037]), and Noori explicitly recognizes the advantages of using multiple transistor unit cells connected in parallel to improve current handling capabilities (Noori, [0007; 0102]). Therefore, it would have been obvious to a person having ordinary skill in the art to arrive at Applicant’s claimed second integrated circuit comprising a second power field-effect transistor and a second sense field-effect transistor because a person having ordinary skill would have recognized that applying the techniques of Noori in view of Klowak to the sensing circuit taught by Hosokawa would have yielded predictable results such as improved current handling and additional sensing capability.
Furthermore, it has been held that mere duplication of parts, as with Applicant’s claimed second integrated circuit comprising a second power field-effect transistor and a second sense field-effect transistor, has no patentable significance unless a new and unexpected result is produced (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP 2144.04(VI)(B)).
Claims 8-11 recite, inter alia, parallel wiring configurations of each of the gate, drain, source, and sense circuits, respectively, with respective die contacts connected to respective package contacts by respective common couplers.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed wiring configurations of each of the gate, drain, source, and sense circuits within the package because, as discussed above, and explicitly recognized by Klowak, it was known in the art to embed multiple chips together within a package (Klowak, [0037]); Noori explicitly recognizes the advantages of using multiple transistor unit cells connected in parallel to improve current handling capabilities (Noori, [0007; 0102]); and Hosokawa explicitly teaches the use of a power field-effect transistor and a sense field-effect transistor connected in parallel (Hosokawa, FIG. 3 and associated text). Therefore, it would have been obvious to a person having ordinary skill in the art to arrive at Applicant’s claimed wiring configurations of each of the gate, drain, source, and sense circuits with respective die contacts connected to respective package contacts by respective common couplers. The motivation for doing so would be, as recognized by Klowak, to provide corresponding source, drain, gate and source sense contacts for electrical connections (Klowak, [0086]) between each of the integrated circuit dies and corresponding package contacts, thereby providing for device functionality. A person having ordinary skill would have recognized that applying the techniques of Noori in view of Klowak to the sensing circuit taught by Hosokawa would have yielded predictable results such as improved current handling and improved sensing capability.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
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/D.L.N./Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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