Prosecution Insights
Last updated: October 04, 2026
Application No. 18/498,031

DUMMY DIES AND METHOD OF FORMING THE SAME

Final Rejection §102§103
Filed
Oct 30, 2023
Priority
Jul 06, 2023 — provisional 63/525,236
Examiner
TRAN, TRANG Q
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
600 granted / 738 resolved
+13.3% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
47 currently pending
Career history
776
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.1%
+7.1% vs TC avg
§102
35.5%
-4.5% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 738 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 21-22, 25-27 and 29 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Karhade et al. (US 2025/0006678, as recited in previous Office action). As for claim 21, Karhade et al. disclose in Figs. 4A-4H and the related text a method, comprising: forming a bonding film 103(1)/105(1) on a first die 110; forming one or more dummy conductors 117 in the first bonding film, wherein the one or more dummy conductors 117 electrically float in the first bonding film (Figs. 4A-4H); bonding a second die (left 114) to the first die via the first bonding film (Fig. 4D-4H); and bonding a dummy die (right 114) to the first die and bonded via the first bonding film (Fig. 4D-4H), wherein dummy die (right 114) comprises: a substrate 402; a thermal conducting layer 403 formed over the substrate (Fig. 4D); and a second bonding film 103(2)/105(2) formed over the thermal conducting layer (Fig. 4D-4H), wherein the second bonding film 103(2)/105(2) is bonded to the first bonding film and the one or more dummy conductors therein (Fig. 4D-4H), the one or more dummy conductors 117 are disposed in a dummy area having a (rectangle) shape similar to the dummy die (Fig. 4D-4H), and the one or more dummy conductors 117 in the first bonding film are in contact with the second bonding film (Fig. 4G-4H). As for claim 22, Karhade et al. disclose the method of claim 21, wherein the thermal conducting layer 403 is a nitrogen containing layer [0092]. As for claim 25, Karhade et al. disclose the method of claim 22, wherein the second bonding film 103(2)/105(2) comprises silicon oxide [0078]. As for claim 26, Karhade et al. disclose the method of claim 25, further comprising an adhesive layer 408 disposed between the substrate 402 and the thermal conducting layer 403. As for claim 27, Karhade et al. disclose the method of claim 26, wherein the adhesive layer 408 comprises silicon oxide ([0032]-[0033]). As for claim 29, Karhade et al. disclose the method of claim 21, wherein the first bonding film 103(1)/105(1) includes a band 113 surrounding (portions) the one or more dummy conductors (Fig. 4H), the band 113 is in contact with an edge region of the dummy die (right 114), and the one or more dummy conductors 117 are disposed within (a portion of) the band (Fig. 4H). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karhade et al.. As for claim 23-24, Karhade et al. disclose the method of claim 22, except wherein the thermal conducting layer has a thickness between about 3k angstroms and about 6k angstroms; the second bonding film has a thickness between about 100 angstrom and 1000 angstroms. It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide the thermal conducting layer has a thickness between about 3k angstroms and about 6k angstroms and the second bonding film has a thickness between about 100 angstrom and 1000 angstroms, in order to optimize the performance of the device. Futhermore, it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). Allowable Subject Matter Claims 10-20 and 30 are allowed. The following is an examiner’s statement of reasons for allowance: “dummy die is free of electronic components and comprises: a semiconductor substrate…and the adjustment layer adheres to a surface of the semiconductor substrate by an adhesive layer”, as recited in claim 10; and “forming a dicing pattern over the bonding film; etching through the bonding film, the adjustment layer, and into the semiconductor substrate using the dicing pattern to form dicing trenches; depositing a protection layer in the dicing trenches and on the bonding film; attaching a carrier wafer to the protection layer; and grinding the semiconductor substrate from a back side to expose the protection layer in the dicing trenches”, as recited in claim 15. Claims 11-14, 16-20 and 30 depend among allowable claims 10 and 15. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant's response filed on 06/17/2026 is acknowledged and is answered as follows. Applicant’s arguments, see pgs. 7-8, with respect to the rejection of claim 21, Karhade does not teach or suggest “forming one or more dummy conductors in the first bonding film, wherein the one or more dummy conductors electrically float in the first bonding film; bonding a second die to the first die via the first bonding film; and bonding a dummy die to the first die and bonded via the first bonding film, wherein dummy die is free of electronic components, the second bonding film is bonded to the first bonding film and the one or more dummy conductors therein, the one or more dummy conductors are disposed in a dummy area having a shape similar to the dummy die, and the one or more dummy conductors in the first bonding film are in contact with the second bonding film” have been fully considered but they are not persuasive in view of the following reasons: First, the limitation “the dummy die is free of electronic components” does not present in claim 21. Second, Figs. 4A-4h of Karhade teach forming one or more dummy conductors 117 in the first bonding film, wherein the one or more dummy conductors 117 electrically float in the first bonding film (Figs. 4A-4H); a second bonding film 103(2)/105(2) formed over the thermal conducting layer (Fig. 4D-4H), wherein the second bonding film 103(2)/105(2) is bonded to the first bonding film and the one or more dummy conductors therein (Fig. 4D-4H), the one or more dummy conductors 117 are disposed in a dummy area having a (rectangle) shape similar to the dummy die (Fig. 4D-4H), and the one or more dummy conductors 117 in the first bonding film are in contact with the second bonding film (Fig. 4G-4H). For above reasons, Karhade still teach the claimed invention. In view of the foregoing reasons, the Examiner believes that all Applicant’s arguments and remarks are addressed. The Examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are sustained and maintained. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached Monday-Thursday (9am-4pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRANG Q TRAN/ Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Oct 30, 2023
Application Filed
Mar 18, 2026
Non-Final Rejection mailed — §102, §103
Jun 17, 2026
Response Filed
Sep 15, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751084
ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
2y 9m to grant Granted Sep 29, 2026
Patent 12733542
THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) PACKAGE EMPLOYING A REDISTRIBUTION LAYER (RDL) INTERPOSER FACILITATING SEMICONDUCTOR DIE STACKING, AND RELATED FABRICATION METHODS
4y 5m to grant Granted Sep 08, 2026
Patent 12733506
SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION
3y 8m to grant Granted Sep 08, 2026
Patent 12726202
LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS
3y 3m to grant Granted Sep 01, 2026
Patent 12721220
Methods of Forming Packages and Resulting Structures
3y 7m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
89%
With Interview (+7.3%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 738 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month