Prosecution Insights
Last updated: April 19, 2026
Application No. 18/498,031

DUMMY DIES AND METHOD OF FORMING THE SAME

Non-Final OA §102§103
Filed
Oct 30, 2023
Examiner
TRAN, TRANG Q
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
88%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
579 granted / 716 resolved
+12.9% vs TC avg
Moderate +7% lift
Without
With
+7.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
34 currently pending
Career history
750
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
45.3%
+5.3% vs TC avg
§102
36.1%
-3.9% vs TC avg
§112
17.3%
-22.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 716 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group II species A (Claims 10-29) in the reply filed on 02/18/2023 is acknowledged. Claims 1-9 cancelled. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/30/2023, 05/05/2025 and 06/12/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 10-14, 21-22, 25-29 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Karhade et al. (US 2025/0006678). As for claim 10, Karhade et al. disclose in Figs. 4A-4H and the related text a method, comprising: bonding a first die 110 to a second die (left 114), wherein the first die comprises a first bonding film 103(1)/105(1), and the second die is bonded to the first bonding film (Fig. 1A); and bonding a dummy die (right 114) to the first die, wherein the dummy die comprises: a substrate 402; an adjustment layer 403 formed over the substrate, wherein the adjustment layer has a thermal conductivity in a range between about 30 W/mK and about 100 W/mK ([0092] teach the adjustment layer comprises silicon nitride as same as the claimed invention, therefore the adjustment layer has a thermal conductivity in a range between about 30 W/mK and about 100 W/mK); and a second bonding film 103(2)/105(2) formed over the adjustment layer, and the first bonding film is bonded to the second bonding film (Fig. 4H). As for claim 11, Karhade et al. disclose the method of claim 10, wherein the adjustment layer comprises silicon nitride or silicon carbide [0092]. As for claim 12, Karhade et al. disclose the method of claim 10, further comprising forming one or more dummy conductors 117 in the first bonding film, wherein bonding the dummy die to the first die 110 comprises placing the dummy die (right 117) over the one or more dummy conductors 117 (Fig. 1H). As for claim 13, Karhade et al. disclose the method of claim 10, wherein bonding the first die 110 to the second die (left 114) and bonding the dummy die (right 114) to the first die is performed simultaneously (Fig. 4H-4G). As for claim 14, Karhade et al. disclose the method of claim 10, further comprising: depositing a dielectric material 115 between the second die and the dummy die (Fig. 4D, [0081] and [0094]); and forming external connectors 122 over the first die [0098], wherein the external connectors and the first bonding film are disposed over opposite sides of the first die (Fig. 4H). As for claim 21, Karhade et al. disclose in Figs. 4A-4H and the related text a method, comprising: forming a bonding film 103(1)/105(1) on a first die 110; bonding a second die (left 114) to the first die via the first bonding film (Fig. 4D-4H); and bonding a dummy die (right 114) to the first die and bonded via the first bonding film (Fig. 4D-4H), wherein dummy die comprises: a substrate 402; a thermal conducting layer 403 formed over the substrate (Fig. 4D); and a second bonding film 103(2)/105(2) formed over the thermal conducting layer, wherein the second bonding film is bonded to the first bonding film (Fig. 4G-4H, [0078]). As for claim 22, Karhade et al. disclose the method of claim 21, wherein the thermal conducting layer 403 is a nitrogen containing layer [0092]. As for claim 25, Karhade et al. disclose the method of claim 22, wherein the second bonding film 103(2)/105(2) comprises silicon oxide [0078]. As for claim 26, Karhade et al. disclose the method of claim 25, further comprising an adhesive layer 408 disposed between the substrate 402 and the thermal conducting layer 403. As for claim 27, Karhade et al. disclose the method of claim 26, wherein the adhesive layer 408 comprises silicon oxide ([0032]-[0033]). As for claim 28, Karhade et al. disclose the method of claim 21, further comprising: one or more dummy conductors 117 formed in the first bonding film 103(1)/105(1), wherein the one or more dummy conductors are in contact with the second bonding film (Fig. 4H). As for claim 29, Karhade et al. disclose the method of claim 28, wherein the first bonding film 103(1)/105(1) includes a band 113 surrounding (portions) the one or more dummy conductors (Fig. 4H), the band 113 is in contact with an edge region of the dummy die (right 114), and the one or more dummy conductors 117 are disposed within (a portion of) the band (Fig. 4H). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karhade et al.. As for claim 23-24, Karhade et al. disclose method of claim 22, wherein the thermal conducting layer has a thickness between about 3k angstroms and about 6k angstroms; and the second bonding film has a thickness between about 100 angstrom and 1000 angstroms. It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide the thermal conducting layer has a thickness between about 3k angstroms and about 6k angstroms and the second bonding film has a thickness between about 100 angstrom and 1000 angstroms, in order to optimize the performance of the device. Futhermore, it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). Allowable Subject Matter Claims 15-20 are allowed. The following is an examiner’s statement of reasons for allowance: “forming a dicing pattern over the bonding film; etching through the bonding film, the adjustment layer, and into the semiconductor substrate using the dicing pattern to form dicing trenches; depositing a protection layer in the dicing trenches and on the bonding film; attaching a carrier wafer to the protection layer; and grinding the semiconductor substrate from a back side to expose the protection layer in the dicing trenches”, as recited in claim 15. Claims 16-20 depend among allowable claim 15. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached Monday-Thursday (9am-4pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRANG Q TRAN/ Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Oct 30, 2023
Application Filed
Mar 06, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
88%
With Interview (+7.4%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 716 resolved cases by this examiner. Grant probability derived from career allow rate.

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