DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I in the reply filed on February 26, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 26, 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 7-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung (US 20100238603 A1).
Regarding claim 1, Chung teaches a capacitor device (Fig 2 capacitor structure 100, [0042]), comprising: a first electrode (Fig 2 first electrode 110, [0042]), disposed on a substrate (Fig 2 substrate 10, [0043]); a second electrode (Fig 2 second electrode 130, [0042]), disposed on the first electrode (Fig 2 first electrode 110, [0042]); an insulating layer (Fig 2 insulation layer 120, [0042]), disposed between the first electrode (Fig 2 first electrode 110, [0042]) and the second electrode (Fig 2 second electrode 130, [0042]); a first dielectric layer (Fig 2 insulation layer 140, [0042]), disposed on the substrate (Fig 2 substrate 10, [0043]) and covering the first electrode (Fig 2 first electrode 110, [0042]), the second electrode (Fig 2 second electrode 130, [0042]) and the insulating layer (Fig 2 insulation layer 120, [0042]); a second dielectric layer (Fig 2 insulation layer 190, [0042]), disposed on the first dielectric layer (Fig 2 insulation layer 140, [0042]); and a third electrode (Fig 2 fourth electrode (Fig 2 third electrode 170, [0042]) 180, [0042]) and a fourth electrode (Fig 2 third electrode 170, [0042]), disposed in the second dielectric layer (Fig 2 insulation layer 190, [0042]) and separated from each other (Fig 2), wherein the third electrode (Fig 2 fourth electrode 180, [0042]) is electrically connected ([0057]) to the first electrode (Fig 2 first electrode 110, [0042]), and the fourth electrode (Fig 2 third electrode 170, [0042]) is electrically connected ([0056]) to the second electrode (Fig 2 second electrode 130, [0042]).
Regarding claim 2, Chung teaches the second electrode (Fig 2 second electrode 130, [0042]) and the insulating layer (Fig 2 insulation layer 120, [0042]) expose a part (a part is exposed to allow for plug 160 to connect electrode 110 to electrode 180, [0057]) of the first electrode (Fig 2 first electrode 110, [0042]).
Regarding claim 7, Chung teaches a material of the second dielectric layer (Fig 2 insulation layer 190, [0042]) comprises a high dielectric constant (high-k) material (high-k material, [0058]).
Regarding claim 8, Chung teaches a buffer layer (not shown insulation layer formed on substrate 10, [0043]) disposed between (the capacitor structure 100 is formed on structures formed on the substrate 10, [0043]) the substrate (Fig 2 substrate 10, [0043]) and the first electrode (Fig 2 first electrode 110, [0042]).
Regarding claim 9, Chung teaches the third electrode (Fig 1 fourth electrode (Fig 2 third electrode 170, [0042]) 180, [0042]) and the fourth electrode (Fig 1 third electrode 170, [0042]) are each a comb-shaped electrode ([0049]).
Regarding claim 10, Chung teaches a first conductive via (Fig 2 plug 160, [0057]) and a second conductive via (Fig 2 plug 150, [0056]), wherein the first conductive via (Fig 2 plug 160, [0057]) is disposed between the first electrode (Fig 2 first electrode 110, [0042]) and the third electrode (Fig 2 fourth electrode 180, [0042]), and the second conductive via (Fig 2 plug 150, [0056]) is disposed between the second electrode (Fig 2 second electrode 130, [0042]) and the fourth electrode (Fig 2 third electrode 170, [0042]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 20100238603 A1), in view of Chen et. al. (US 20220406768 A1).
Regarding claim 3, Chung fails to teach a cap layer disposed between the first dielectric layer and the first electrode, between the first dielectric layer and the second electrode, and between the first dielectric layer and the insulating layer.
However, Chen teaches a cap layer (Fig 1 cap layer 84, [0038]) disposed between the first dielectric layer (Fig 1 ILD 50, [0042] corresponds to Chung: Fig 2 insulation layer 140, [0042]) and the first electrode (Fig 1 conductive layer 20B, [0033] corresponds to Chung: Fig 2 first electrode 110, [0042]), between the first dielectric layer (Fig 1 ILD 50, [0042] corresponds to Chung: Fig 2 insulation layer 140, [0042]) and the second electrode (Fig 1 conductive layer 20A corresponds to Chung: Fig 2 second electrode 130, [0042]), and between the first dielectric layer (Fig 1 ILD 50, [0042] corresponds to Chung: Fig 2 insulation layer 140, [0042]) and the insulating layer (Fig 1 dielectric layer 20C corresponds to Chung: Fig 2 insulation layer 120, [0042]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung to incorporate the teachings of Chen by having a cap layer between a dielectric layer and the layers of a capacitor structure. This would alleviate the affection of external force applied ([0039]).
Regarding claim 4, Chung as modified in claim 3 teaches a material of the cap layer (Chen: Fig 1 cap layer 84, [0038]) comprises silicon nitride (SiN) (silicon nitride, [0039]), silicon carbonitride (SiCN) or silicon oxynitride (SiON).
Regarding claim 5, Chung fails to teach an etching stop layer disposed between the first dielectric layer (Fig 2 insulation layer 140, [0042]) and the second dielectric layer (Fig 2 insulation layer 190, [0042]).
However, Chen teaches an etching stop layer (Fig 1 and 6A etch stop layer 82, [0032]) disposed between the first dielectric layer (Fig 1 and 6A ILD layer 81, [0032] corresponds to Chung: Fig 2 insulation layer 140, [0042]) and the second dielectric layer (Fig 1 and 6A dielectric material 14c, [0030] corresponds to Chung: Fig 2 insulation layer 190, [0042]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung to incorporate the teachings of Chen by having an etch stopping layer between dielectric layers. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the etch stop layer is used to protect the material underneath during etch processes. Thus, one having ordinary skill in the art before the effective filing date of the claimed invention would be motivated to provide additional protection to the underlying dielectric layer and plugs during the etching to form trenches for the top electrodes.
Regarding claim 6, Chung as modified in claim 5 teaches the third electrode (Chung: Fig 2 fourth electrode (Fig 2 third electrode 170, [0042]) 180, [0042]) and the fourth electrode (Chung: Fig 2 third electrode 170, [0042]) extend into the etching stop layer (Chen: Fig 1 and 6A etch stop layer 82, [0032]).
Examiner notes the electrodes would need to extend into the etch stopping layer so that the third and fourth electrodes can make electrical contact with the underlying plugs.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sasaki (US 7230434 B1) teaches structure broadly.
Harjani et. al. (US 20170301675 A1) teaches a similar structure but with stacked comb electrodes.
Fujimoto et al. (US 20140152379 A1) teaches a similar structure but with stacked comb electrodes.
Hsu et. al. (US 20070102745 A1) teaches a similar structure but with stacked comb electrodes.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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