CTNF 18/498,293 CTNF 89200 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/31/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Group II (claims 15-34) in the reply filed on 03/17/2026 is acknowledged. 08-06 AIA Claim s 1-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected Group I , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/17/2026 . Claim Objections 07-29-01 AIA Claim 21 is objected to because of the following informalities: Claim 21 recites “the nanostructures” in line 6. Although, it is understood to be referring to the plurality of nanostructures, as introduced the line before, the Office suggests amending the claim to have identical reference names . Appropriate correction is required. 07-29-01 AIA Claim 23 is objected to because of the following informalities: Claim 23 recites “the nanostructures” in line 5. Although, it is understood to be referring to the plurality of nanostructures, as introduced the line before, the Office suggests amending the claim to have identical reference names . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. With regards to claim 15 (and all dependent claims thereof) it is unclear how one would remove the portion of the protection layer prior to filling the opening with the protection layer? Note: all dependent claims necessarily inherit the indefiniteness of the claims from which they depend. Prior Art 07-96 AIA 1. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : a. Wu et al. (PG Pub 2026/0156913) teaches a semiconductor structure. b. Lin et al. (PG Pub 2025/0324663) teaches a method of forming a semiconductor structure. c. Chiang et al. (PG Pub 2025/0142893) teaches a semiconductor structure. d. Chen et al. (PG Pub 2024/0313047) teaches a semiconductor device. e. Su et al. (PG Pub 2021/0399109) teaches a semiconductor structure . Allowable Subject Matter 07-43-01 AIA 2. Claim s 15-24 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action. Claims 25-34 are allowable. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claim 25 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 25 , forming a first stack structure and a second stack structure along a first direction over a first region and a second region of a substrate, respectively, wherein the first stack structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked, and the second stack structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked; forming a first dummy gate structure along a second direction over the first stack structure and the second stack structure in the first region; forming a second dummy gate structure over the first stack structure and the second stack structure along the second direction in the second region; removing a portion of the first dummy gate structure to form a trench in the first region and removing a portion of the second dummy gate structure to form an opening in the second region, wherein the trench in the first region has a first length along the second direction, and the opening in the second region has a second length along the second direction, and the first length is greater than the second length; forming a protection layer in the trench in the first region; simultaneously forming the protection layer in the opening in the second region to form a dielectric wall structure between the first stack structure and the second stack structure; and forming a filling layer on the protection layer in the first region to form a dielectric strip structure in the first region, wherein the dielectric strip structure comprises the protection layer and the filling layer surrounded by the protection layer. Claims 26-29 would be allowable, because they depend on allowable claim 25 . Claim 30 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 30 , forming a first stack structure and a second stack structure along a first direction over a first region and a second region of a substrate, respectively, forming a first dummy gate structure along a second direction over the first stack structure and the second stack structure in the first region, wherein the first dummy gate structure comprises a dummy gate dielectric layer; forming a second dummy gate structure over the first stack structure and the second stack structure along the second direction in the second region ;removing a portion of the first dummy gate structure to form a trench in the first region and removing a portion of the second dummy gate structure to form an opening in the second region, wherein the dummy gate dielectric layer of the first dummy gate structure is exposed by the trench; forming a protection layer in the trench in the first region; simultaneously forming the protection layer in the opening in the second region to form a dielectric wall structure between the first stack structure and the second stack structure; removing a portion of the protection layer, a portion of the first stack structure and a portion of the second stack structure to form a recess in the first region, wherein a bottom surface of the recess is lower than a bottom surface of the dummy gate dielectric layer; and forming a filling layer in the recess in the first region to form a dielectric strip structure in the first region. Claims 31-34 would be allowable, because they depend on allowable claim 30. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817 Application/Control Number: 18/498,293 Page 2 Art Unit: 2817 Application/Control Number: 18/498,293 Page 3 Art Unit: 2817 Application/Control Number: 18/498,293 Page 4 Art Unit: 2817 Application/Control Number: 18/498,293 Page 5 Art Unit: 2817 Application/Control Number: 18/498,293 Page 6 Art Unit: 2817 Application/Control Number: 18/498,293 Page 7 Art Unit: 2817
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