DETAILED ACTION
This action is responsive to the Amendments filed June 6, 2026. Claims 1-19, and 21 are pending. Claims 1 and 21 are amended. Claims 1, 11, and 21 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is objected to under 37 CFR 1.72(a) because it is not descriptive of the invention claimed and disclosed.
By the present amendment, the title has been changed to “MEMORY CELL WITH TRANSMISSION GATE”. While the amendment removes the wholly non-descriptive original title, the amended title remains deficient.
The entire disclosure of the instant application is directed exclusively to an 8T static random-access memory (SRAM) cell that employs complementary transmission pass-gates with one word line routed on the front-side and the complementary word line routed on the back-side.
The amended title omits any identification of the invention as an SRAM cell – the only type of memory cell disclosed – and fails to reflect the distinctive structural features that define the contribution. As a result, the title remains non-descriptive of the invention as claimed and disclosed and the objection to the title is maintained. See MPEP § 606.01.
Response to Amendment
Applicant's amendments to claims 1 and 21 reversing the signal names in the "wherein" clauses so that they match the structural coupling is acknowledged and accepted. The rejection under 35 U.S.C. § 112(b) for indefiniteness for the structural connectivity mismatch of the word lines of claims 1 and 21 in the previous Office action is withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 21, each recite (emphasis added):
"a read word line … being on a first metal layer above a front-side of a substrate, and the read word line being on top of at least one of the first transmission pass-gate or the second transmission pass-gate, and being coupled to the first pass-gate transistor and the third pass-gate transistor," and "a write word line … being on a second metal layer below a back-side of the substrate …, and the write word line being underneath at least one of the first transmission pass-gate or the second transmission pass-gate, and being coupled to the second pass-gate transistor and the fourth pass-gate transistor."
The phrases "on top of … the … transmission pass-gate" and "underneath … the … transmission pass-gate" render the claims indefinite.
Each transmission pass-gate is defined as a vertically stacked pair of transistors of opposite conductivity types. The claims provide no guidance as to:
What portion or boundary of the “transmission pass-gate” serves as the reference for the spatial relationship (the upper transistor only, both transistors, the gate electrodes, the active regions, the highest or lowest point of the stacked structure, etc.);
Whether any lateral overlap or registration between the word-line metal and the footprint of the pass-gate is required, or whether a purely vertical relationship (any metal on a higher or lower layer) is sufficient; and
The degree of any required overlap (partial, substantial, complete, or overlap limited to a specific feature such as a gate electrode).
The specification does not define or clarify these terms. It describes the read word line as being on a metal layer above the front-side of the substrate and the write word line as being on a metal layer below the back-side of the substrate, and it shows vertical stacking of the complementary pass-gate transistors, but it never uses the phrases “on top of the transmission pass-gate” or “underneath the transmission pass-gate,” nor does it establish any required lateral relationship between the word-line metals and the pass-gate structures. Although Figs. 4A-4G are cross-sectional views that generally depict the front-side metal layer above the stacked pass-gate transistors and the back-side metal layer below those transistors, the figures do not define the degree of lateral overlap or registration (if any) required between the word line metals and the transmission pass-gates, nor do they establish the precise reference boundary of the "transmission pass-gate" for purposes of "on top of" and "underneath" limitations. Drawings alone cannot cure the indefiniteness of relative spatial language that lacks a clear standard in the written description. See MPEP § 2173.05(b).
A person of ordinary skill in the art therefore cannot determine the metes and bounds of the claimed invention with reasonable certainty. It is unclear, for example, whether a front-side metal line that runs parallel to but laterally offset from a transmission pass-gate (zero footprint overlap) would satisfy the “on top of” limitation, or whether only a metal line that partially or fully overlies a gate electrode or active region of the pass-gate would infringe.
As per MPEP § 2173.06, for purposes of applying prior art, and consistent with the practice of compact prosecution, these phrases will be interpreted consistent with the specification to require only that:
the read word line is located on a metal layer that is vertically above the transmission pass-gate structure, and
the write word line is located on a metal layer that is vertically below the transmission pass-gate structure.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
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Claims 1-2, 7, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. ("Implementation of High Performance SRAM Cell Using Transmission Gate"; “Sharma” – of record) in view Chiu et al. (US 20210343332; “Chiu”)
Regarding independent claim 1, notwithstanding the indefiniteness rejection above, Sharma discloses a memory cell, comprising:
a first (second) transmission pass-gate comprising:
a first (third) pass-gate transistor of a first type (Fig. 1);
and a second (fourth) pass-gate transistor of a second type different from the first type (Fig.1),
and the second (fourth) pass-gate transistor being below the first (third) pass-gate transistor (Fig. 1. It is noted that the specification of the instant application declares that the spatially relative term "below" be defined “to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures (para. 20) of which the schematics are not excluded. Moreover, even in light of a physical layout interpretation, the vertical stacking is a conventional CFET-style arrangement of opposite-type transistors in a transmission gate. The structural relationship of one transistor of the first type and one of the second type in a transmission pass-gate is taught by Sharma. To the extent that a specific vertical orientation is required, it would have been an obvious design choice.)
wherein the first pass-gate transistor and the third pass-gate transistor are turned on in response to the read word line signal during a write operation (Fig. 1 where it illustrates that interconnect line WL would turn on the two NFET transistors 1 and 3 when it is a logic 1.);
and the second pass-gate transistor and the fourth pass-gate transistor are turned on in response to the write word line signal during the write operation after the first pass-gate transistor and the third pass-gate transistor are turned on (Fig. 1 where it illustrates that interconnect line WLB would turn on the two PFET transistors 2 and 4 when it is a logic 0. Note that as per MPEP 2114(II), in an apparatus claim, the manner of operating a device does not differentiate from the prior art. The limitation in this claim regarding the timing of turning on the transistors (second and fourth turned on after first and third) is directed to the manner of operating the SRAM memory cell and does not include any further apparatus limitations to distinguish the claimed apparatus from Sharma’s apparatus, nor are any means which would control the timing of the word line signals explicitly disclosed. Thus, it does not differentiate from Sharma. It is suggested that any “manner of operating” limitations be redrafted in method form.)
(and a write word line…) being coupled to the second pass-gate transistor and the fourth pass-gate transistor, being configured to receive a write word line signal (Fig. 1),
Sharma discloses a memory cell having first and second complementary transmission pass-gates (each comprising a first-type transistor and a second-type transistor of opposite conductivity) and two word line signals that control the opposite polarities of those transmission gates. Sharma is silent with respect to placing one of those word-line signals on a metal layer above a front-side of a substrate and the complementary word line signal on a metal layer below a back-side of the substrate.
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However, Chiu teaches a read word line extending in a first direction (Fig. 7 where it illustrates WL 310 extending in a first direction), being on a first metal layer above a front-side of a substrate and the read word line being on top of at least one of the first transmission pass-gate or the second transmission pass-gate, and being coupled to the first pass-gate transistor and the third pass-gate transistor, and being configured to receive a read word line signal (Fig. 8C. See also para. 45; "The metal line 714D is connected down through via feature 712D and contact feature 710D to the gate electrode of the pass-gate device (PG-1) and connected up to the word-line (WL), therefore also being referred by WL".);
and a write word line extending in the first direction (Fig. 7 where it illustrates WLB 310 extending in a first direction), being on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and the write word line being underneath at least one of the first transmission pass-gate or the second transmission pass-gate (Fig. 8C. See also para 46; “The metal line 722C is connected through via feature 720C to the gate electrode of the pass-gate device (PG-2) as the complimentary word-line (WLB)”),
and being separated from the read word line in a second direction different from the first direction (Fig. 7 where it illustrates the WL and WLB are separated from each other by a second direction);
Sharma and Chiu are from the same field of endeavor as applicant’s invention directed to SRAM memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Chiu’s known technique of routing complementary word lines on opposite sides of the substrate to the dual word line signals already present in Sharma’s complementary transmission gate SRAM cell. Doing so would result in a predictable layout arrangement which improves routing density and reduces metal resistance and parasitic capacitance.
Regarding claim 2, Sharma and Chiu combined disclose the limitations of claim 1.
As applied, Sharma further discloses further comprising
a first inverter coupled to the first pass-gate transistor, the second pass-gate transistor, the third pass-gate transistor and the fourth pass-gate transistor (Fig. 1);
and a second inverter coupled to the first pass-gate transistor, the second pass-gate transistor, the third pass-gate transistor and the fourth pass-gate transistor (Fig. 1).
Regarding claim 7 and 12, Sharma and Chiu combined disclose the limitations of claims 1 and 11 respectively.
As applied, Sharma further discloses wherein the first pass-gate transistor comprises:
a first gate extending in the second direction and being on a first level (Fig. 1);
the second pass-gate transistor comprises:
a second gate extending in the second direction, and being on a second level below the first level (Fig. 1. It is noted that the instant application defines the term "below" only as it relates to positional relationship as illustrated in the figures (para. 20), therefore this limitation is understood using the broadest reasonable interpretation to mean that second direction is “up and down on the page” and the second gate is below the first gate as illustrated in Fig. 1)
the third pass-gate transistor comprises:
a third gate extending in the second direction, being separated from the first gate in the second direction, and being on the first level (Fig. 1);
and the fourth pass-gate transistor comprises:
a fourth gate extending in the second direction, being separated from the second gate in the second direction, and being on the second level (Fig. 1. Id and for the same reasons as above).
Regarding independent claim 11, Sharma discloses a memory cell, comprising
a first transmission pass-gate comprising:
a first pass-gate transistor of a first type (Fig. 1);
and a second pass-gate transistor of a second type different from the first type, and the second pass-gate transistor being below the first pass-gate transistor (Fig. 1);
a second transmission pass-gate comprising:
a third pass-gate transistor of the first type (Fig. 1);
and a fourth pass-gate transistor of the second type, the fourth pass-gate transistor being below the third pass-gate transistor (Fig. 1);
wherein the first pass-gate transistor and the third pass-gate transistor are turned on at a first time in response to the write word line signal during a write operation; (Fig. 1 where it illustrates that interconnect line WL would turn on the two NFET transistors 1 and 3 when it is a logic 1. It appears this limitation is directed to Fig. 2B of the instant application.)
and the second pass-gate transistor and the fourth pass-gate transistor are turned on at a second time in response to the read word line signal during the write operation, (Fig. 1 where it illustrates that interconnect line WLB would turn on the two PFET transistors 2 and 4 when it is a logic 0.)
the first time being before the second time (Fig. 1. Sharma's structure is identical to that of the instant application. And as per MPEP 2114(II), in an apparatus claim, the manner of operating a device does not differentiate from the prior art. The limitation in this claim regarding the timing of turning on the transistors is directed to the manner of operating the SRAM memory cell and does not include any further apparatus limitations to distinguish the claimed apparatus from Sharma’s apparatus, nor are there any means which would control the timing of the word line signals explicitly disclosed. Thus, it does not differentiate from Sharma. It is suggested that any “manner of operating” limitations be redrafted in method form).
Sharma discloses a memory cell having first and second complementary transmission pass-gates (each comprising a first-type transistor and a second-type transistor of opposite conductivity) and two word line signals that control the opposite polarities of those transmission gates. Sharma is silent with respect to placing one of those word-line signals on a metal layer above a front-side of a substrate and the complementary word line signal on a metal layer below a back-side of the substrate.
However, Chiu teaches a write word line extending in a first direction (Fig. 7 where it illustrates WL 310 extending in a first direction), being on a first metal layer above a front- side of a substrate, being coupled to the first pass-gate transistor and the third pass-gate transistor, and being configured to receive a write word line signal (Fig. 8C. See also para. 45; "The metal line 714D is connected down through via feature 712D and contact feature 710D to the gate electrode of the pass-gate device (PG-1) and connected up to the word-line (WL), therefore also being referred by WL". It is noted that the structural arrangement of the word line labels of claim 1 are reversed for claim 11. Chiu expressly teaches that either of the complementary word lines may be formed on the front-side and the other on the back-side (“or vice versa”) The flipped assignment is therefore an obvious variation already contemplated by Chiu and does not patentably distinguish claim 11 from the combination applied to claim 1.);
and a read word line extending in the first direction (Fig. 7 where it illustrates WLB 310 extending in a first direction), being on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and the read word line being coupled to the second pass-gate transistor and the fourth pass-gate transistor, being configured to receive a read word line signal (Fig. 8C. See also para 46; “The metal line 722C is connected through via feature 720C to the gate electrode of the pass-gate device (PG-2) as the complimentary word-line (WLB)”),
and being separated from the write word line in a second direction different from the first direction (Fig. 7 where it illustrates the WL and WLB are separated from each other by a second direction);
Sharma and Chiu are from the same field of endeavor as applicant’s invention directed to SRAM memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Chiu’s known technique of routing complementary word lines on opposite sides of the substrate to the dual word line signals already present in Sharma’s complementary transmission gate SRAM cell. Doing so would result in a predictable layout arrangement which improves routing density and reduces metal resistance and parasitic capacitance.
Claims 3-4, 16-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. ("Implementation of High Performance SRAM Cell Using Transmission Gate"; “Sharma” – of record) in view of Chiu et al. (US 20210343332; “Chiu”) and further in view of Nii et al. (US 6627960; “Nii” – of record).
Regarding claims 3 and 16, Sharma and Chiu disclose the limitations of claim 2 and 11 respectively.
As applied, Sharma further discloses further comprising:
(a bit line…) and being coupled to the first transmission pass-gate (Fig. 1);
(a bit line bar…) and being coupled to the second transmission pass-gate (Fig. 1);
Sharma and Chiu combined are silent with respect to the particular arrangement of bit line conductors as claimed.
However, Nii teaches a bit line extending in the first direction, being configured to receive a bit line signal, being on the first metal layer (Fig. 19: AL17 where it illustrates the first bit line (BL11) of the cross coupled inverter SRAM cell layout being on the first metal layer),
and a bit line bar extending in the first direction, being configured to receive a bit line bar signal, being on the first metal layer (Fig. 19: AL18 where it illustrates the second bit line (BL12) of the cross coupled inverter SRAM cell layout being on the first metal layer),
Sharma and Chiu combined as well as Nii are from the same field of endeavor as applicant’s invention directed to SRAM memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharma’s circuit topology and the teachings of Chiu’s physical layout to utilize both frontside and backside connectivity with the teachings of Nii’s layout of a cross-coupled inverter SRAM cell. Doing so would result in a compact base memory component which could be highly replicated to form a noise tolerant SRAM array.
Regarding claims 4 and 17, Sharma, Chiu and Nii combined disclose the limitations of claim 3 and 16 respectively.
As applied, Sharma further discloses wherein
the bit line comprises:
and being coupled to the first pass-gate transistor and the second pass-gate transistor (Fig. 1 BL);
and the bit line bar comprises:
being coupled to the third pass-gate transistor and the fourth pass-gate transistor (Fig. 1 BLB),
As applied, Nii further discloses
(the bit line comprises:) a first conductor extending in the first direction, being configured to receive the bit line signal, being on the first metal layer (Fig. 19: AL17 where it illustrates the first bit line (BL11) of the cross coupled inverter SRAM cell layout being on the first metal layer),
(and the bit line bar comprises:) a second conductor extending in the first direction, being configured to receive the bit line bar signal, being on the first metal layer (Fig. 19: AL18 where it illustrates the second bit line (BL12) of the cross coupled inverter SRAM cell layout being on the first metal layer),
and being separated from the first conductor in the second direction (Fig. 19 where it illustrates the lines AL17 and AL18 being separated by a distance in a second direction).
Regarding independent claim 21, notwithstanding the indefiniteness rejection above, Sharma discloses a memory cell, comprising:
a first (second) transmission pass-gate comprising:
a first (third) pass-gate transistor of a first type (Fig. 1);
and a second (fourth) pass-gate transistor of a second type different from the first type (Fig.1),
and the second (fourth) pass-gate transistor being below the first (third) pass-gate transistor (Fig. 1. It is noted that the specification of the instant application declares that the spatially relative term "below" be defined “to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures (para. 20) of which the schematics are not excluded. Moreover, even in light of a physical layout interpretation, the vertical stacking is a conventional CFET-style arrangement of opposite-type transistors in a transmission gate. The structural relationship of one transistor of the first type and one of the second type in a transmission pass-gate is taught by Sharma. To the extent that a specific vertical orientation is required, it would have been an obvious design choice.
and the read word line being coupled to the first pass-gate transistor and the third pass-gate transistor (Fig. 1 where it illustrates interconnect line WL coupled to the first and third transistors),
(a write word line…) being coupled to the second pass-gate transistor and the fourth pass-gate transistor (Fig. 1 where it illustrates interconnect line WLB coupled to the second and forth transistors),
(a bit line…) and being coupled to the first transmission pass-gate; (Fig. 1)
(a bit line bar…) and being coupled to the second transmission pass-gate (Fig. 1);
wherein the first pass-gate transistor and the third pass-gate transistor are turned on in response to the read word line signal during a write operation (Fig. 1 where it illustrates that interconnect line WL would turn on the two NFET transistors 1 and 3 when it is a logic 1. As noted in the indefiniteness rejection above, this element is interpreted to refer to the read word line (RWWL) in the instant application as it appears this limitation is directed to Fig. 2A of the instant application);
and the second pass-gate transistor and the fourth pass-gate transistor are turned on in response to the write word line signal during the write operation after the first pass-gate transistor and the third pass-gate transistor are turned on (Fig. 1 where it illustrates that interconnect line WLB would turn on the two PFET transistors 2 and 4 when it is a logic 0. As noted in the indefiniteness rejection above, this element is interpreted to refer to the write word line (WWL) in the instant application. Additionally, Sharma's structure is identical to that of the instant application. And as per MPEP 2114(II), in an apparatus claim, the manner of operating a device does not differentiate from the prior art. The limitation in this claim regarding the timing of turning on the transistors is directed to the manner of operating the SRAM memory cell and does not include any further apparatus limitations to distinguish the claimed apparatus from Sharma’s apparatus, nor are there any means which would control the timing of the word line signals explicitly disclosed. Thus, it does not differentiate from Sharma. It is suggested that any “manner of operating” limitations be redrafted in method form.)
Sharma discloses a memory cell having first and second complementary transmission pass-gates (each comprising a first-type transistor and a second-type transistor of opposite conductivity) and two word line signals that control the opposite polarities of those transmission gates. Sharma is silent with respect to placing one of those word-line signals on a metal layer above a front-side of a substrate and the complementary word line signal on a metal layer below a back-side of the substrate.
However, Chiu teaches a read word line extending in a first direction (Fig. 7 where it illustrates WL 310 extending in a first direction), being on a first metal layer above a front-side of a substrate and the word line being on top of at least one of the first transmission pass-gate or the second transmission pass-gate (Fig. 8C. See also para. 45; "The metal line 714D is connected down through via feature 712D and contact feature 710D to the gate electrode of the pass-gate device (PG-1) and connected up to the word-line (WL), therefore also being referred by WL".),
and being configured to receive a read word line signal (merely functional language describing intended use of the already mapped word line structures and therefore analogous to the combination of Sharma and Chiu),
a write word line extending in the first direction (Fig. 7 where it illustrates WLB 310 extending in a first direction), being on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and the write word line being underneath at least one of the first transmission pass-gate or the second transmission pass-gate (Fig. 8C. See also para 46; “The metal line 722C is connected through via feature 720C to the gate electrode of the pass-gate device (PG-2) as the complimentary word-line (WLB)”),
being configured to receive a write word line signal (merely functional language describing intended use of the already mapped word line structures and therefore analogous to the combination of Sharma and Chiu),
and being separated from the read word line in a second direction different from the first direction (Fig. 7 where it illustrates the WL and WLB are separated from each other by a second direction);
direction (Fig. 7 where it illustrates WL 310 extending in a first direction), being on a first metal layer above a front-side of a substrate and the read word line being on top of at least one of the first transmission pass-gate or the second transmission pass-gate, and being coupled to the first pass-gate transistor and the third pass-gate transistor, and being configured to receive a read word line signal (Fig. 8C. See also para. 45; "The metal line 714D is connected down through via feature 712D and contact feature 710D to the gate electrode of the pass-gate device (PG-1) and connected up to the word-line (WL), therefore also being referred by WL".);
and a write word line extending in the first direction (Fig. 7 where it illustrates WLB 310 extending in a first direction), being on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and the write word line being underneath at least one of the first transmission pass-gate or the second transmission pass-gate (Fig. 8C. See also para 46; “The metal line 722C is connected through via feature 720C to the gate electrode of the pass-gate device (PG-2) as the complimentary word-line (WLB)”),
and being separated from the read word line in a second direction different from the first direction (Fig. 7 where it illustrates the WL and WLB are separated from each other by a second direction);
Sharma and Chiu combined are silent with respect to the particular arrangement of bit line conductors as claimed.
However, Nii teaches a bit line extending in the first direction, being configured to receive a bit line signal, being on the first metal layer (Fig. 19: AL17 where it illustrates the first bit line (BL11) of the cross coupled inverter SRAM cell layout being on the first metal layer),
and a bit line bar extending in the first direction, being configured to receive a bit line bar signal, being on the first metal layer (Fig. 19: AL18 where it illustrates the second bit line (BL12) of the cross coupled inverter SRAM cell layout being on the first metal layer),
Sharma and Chiu combined as well as Nii are from the same field of endeavor as applicant’s invention directed to memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharma’s circuit topology and the teachings of Chiu’s physical word line layout to utilize both frontside and backside connectivity with the teachings of Nii’s layout of a cross-coupled inverter SRAM cell. Doing so would result in a compact base memory component which could be highly replicated to form a noise tolerant SRAM array.
Claims 8-10 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. ("Implementation of High Performance SRAM Cell Using Transmission Gate"; “Sharma” – of record) in view of Chiu et al. (US 20210343332; “Chiu”) and further in view of Nebesnyi (US 9514264 – of record)
Regarding claims 8 and 13, Sharma and Chiu combined disclose the limitations memory of claims 7 and 12 respectively.
Sharma and Chiu are silent with respect to explicit gate isolation in the physical layout.
However, Nebesnyi teaches further comprising:
a first gate isolation layer between the first gate and the second gate; and a second gate isolation layer between the third gate and the fourth gate (Fig. 1B where it illustrates a first gate (176), and a second gate (186) separated by a distance. It is well known in the art that there is a dielectric layer between polysilicon gates).
Sharma and Chiu combined as well as Nebesnyi are from the same field of endeavor as applicant’s invention directed to integrated circuits useful in memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharma’s circuit topology and the teachings of Chiu’s physical layout to utilize both frontside and backside connectivity with the teachings of Nebesnyi’s layout of a transmission gate which can be used in an TG8T SRAM cell. Doing so would result in a compact base memory component which could be highly replicated to form a noise tolerant SRAM array.
Regarding claims 9 and 14, Sharma, Chiu and Nebesnyi combined disclose the limitations memory of claims 8 and 13 respectively.
As applied, Nebesnyi further discloses wherein the read word line comprises:
a first conductor extending in the first direction, being coupled to the first pass-gate transistor, being on the first metal layer, and overlapping the first gate (Fig. 1B where it illustrates the first gate (176) of the first pass-gate transistor, which has a contact to a metal 1 stub (first conductor) overlapping the first gate. See also col.6, ln. 41-45; "The poly gate pattern 176 is coupled (e.g., through a contact, a metal 1 stub", "to the metal line 174a", "which forms a portion of the control terminal 102 and carries the corresponding control signal." It is noted that control terminal 102 is analogous to the RWWL signal of the instant application);
and a second conductor extending in the first direction, being coupled to the third pass-gate transistor, being on the first metal layer, being separated from the first conductor in the second direction, and overlapping the third gate (Fig. 1B, third gate (196) with the same reasoning as above);
and the write word line comprises:
a third conductor extending in the first direction, being coupled to the second pass-gate transistor, being on the second metal layer, and being overlapped by the second gate (Fig. 1B where it illustrates the second gate (186, section 122) of the second pass-gate transistor which is coupled to the metal 2 line (104) which overlaps the second gate. See also col. 6, ln. 55-60; "The poly gate pattern 186 is coupled (e.g., through a contact, a metal 1 stub, and a via between metal 1 and metal 2 layers) to the metal line 188a (e.g., at metal 2 layer), which forms at least a portion of the control terminal 104 and carries the corresponding control signal." It is noted that control terminal 104 is analogous to the WWL signal of the instant application);
and a fourth conductor extending in the first direction, being coupled to the fourth pass-gate transistor, being on the second metal layer, being separated from the third conductor in the second direction, and being overlapped by the fourth gate (Fig. 1B, fourth gate (186, section 132) with the same reasoning as above).
Regarding claims 10 and 15, Sharma, Chiu and Nebesnyi combined disclose the limitations memory of claims 9 and 14 respectively.
As applied, Nebesnyi further discloses further comprising:
a first via electrically coupling the first conductor and the first gate together, the first via being between the first conductor and the first gate (Fig. 1B, the via between control line (102) and the first gate (176));
a second via electrically coupling the third conductor and the second gate together, the second via being between the third conductor and the second gate (Fig. 1B, the via between control line (102) and the second gate (196));
a third via electrically coupling the second conductor and the third gate together, the third via being between the second conductor and the third gate (Fig. 1B, the via between control line (104) and the third gate (186, section 122));
and a fourth via electrically coupling the fourth conductor and the fourth gate together, the fourth via being between the fourth conductor and the fourth gate (Fig. 1B, the via between control line 104 and the fourth gate (186, section 132). It is noted that the third and fourth via regions are effectively shared as the control line (104) is also effectively shared due to a routine design choice to combine and is electrically analogous to the instant application as the same control line is shared by the third and fourth transistors in the instant application).
Claims 5-6 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. ("Implementation of High Performance SRAM Cell Using Transmission Gate"; “Sharma” – of record) in view of Chiu et al. (US 20210343332; “Chiu”) and further in view of Nii et al. (US 6627960; “Nii” – of record) and further in view of Nebesnyi (US 9514264 – of record)
Regarding claims 5 and 18, Sharma, Chiu and Nii combined disclose the limitations memory of claims 4 and 17 respectively.
Sharma, Chiu and Nii are silent with respect to the explicit physical layout of the transmission gates.
However, Nebesnyi teaches further comprising:
a first contact extending in the second direction (Fig. 1B. See also col. 6, ln. 61-62; "In the layout of the transmission gate 150 in FIG. 1B, one pair of diffusion terminals 116 and 126 of the FETs 110 and 120 (of the transmission gate in Fig. 1A), respectively, are coupled through a connection 180, for example, at the metal 1 layer. It is well known in the art that a contact is used to connect metal 1 to diffusion"),
and being electrically coupled to a source/drain of the first pass-gate transistor and a source/drain of the second pass-gate transistor (Fig. 1 where it shows the signal QB connected to the drain/source of the first and second pass-gate transistors);
and a second contact extending in the second direction (Fig. 1B. See also col. 7, ln. 36-39; "In the layout of the transmission gate 160 in FIG. 1B, one pair of diffusion terminals 136 and 146 of the FETs 130 and 140, respectively, are coupled through a connection 192 for example, at the metal 1 layer. It is well known in the art that a contact is used to connect metal 1 to diffusion"),
and being electrically coupled to a source/drain of the third pass-gate transistor and a source/drain of the fourth pass-gate transistor (Fig. 1 where it shows the signal Q connected to the drain/source of the third and second pass-gate transistors),
and being separated from the first contact in at least the first direction or the second direction (Fig. 1B where it shows the contacts for line 180 and 192 being separated by a distance in the second direction).
Sharma, Chiu and Nii combined as well as Nebesnyi are from the same field of endeavor as applicant’s invention directed to integrated circuits useful in memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharma’s circuit topology and the teachings of Chiu’s physical layout to utilize both frontside and backside connectivity with the teachings of Nii’s layout of a cross-coupled inverter SRAM cell with Nebesnyi’s layout of a transmission gate which can all be used in an TG8T SRAM cell. Doing so would result in a compact base memory component which could be highly replicated to form a noise tolerant SRAM array.
Regarding claims 6 and 19, Sharma, Chiu and Nii combined disclose the limitations memory of claims 5 and 18 respectively.
Sharma, Chiu and Nii are silent with respect to the explicit physical layout of the transmission gates.
However, Nebesnyi teaches further comprising:
a first via electrically coupling the first conductor and the first contact together (Fig. 1B where it illustrates vias connecting to metal 2 and contacts to diffusion. It is noted that the term "contact" is defined in the instant application as a "metal over diffusion" layer for which a contact cut region to diffusion is created. This structure is apparently directed to the bit line or bit line bar input to the transmission gates of Fig. 2A of the instant application. It is noted that while Nebesnyi's layout diagram does not explicitly indicate connection of the transmission gate input above metal 1for sake of brevity, doing so would merely be a routine design choice),
the first via being between the first conductor and the first contact (Fig. 1B where it illustrates vias connecting to metal 2 and contacts to diffusion. It is well understood in the art that the via layer connects metal 2 to the poly or metal 1 layer);
and a second via electrically coupling the second conductor and the second contact together, the second via being between the second conductor and the second contact (Id and for the same reason).
Response to Arguments
Applicant’s arguments with respect to claims 1, 11, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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