DETAILED ACTION
This action is responsive to the reply to the Requirement for Restriction filed February 21, 2024. Claims 1-20 are pending. Claim 20 has been cancelled. Claim 21 is new. Upon entry Claims 1-19 and 20 are pending. Claims 1, 11, and 21 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on November 13, 2024. This IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of Group I – Claims 1-19 in the reply filed on September 8, 2025, is acknowledged. Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SRAM Memory Cell using Transmission Gate.
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claims 1 and 21, the limitation “wherein the first pass-gate transistor and the third pass-gate transistor are turned on in response to the write word line signal” is unclear because an antecedent limitation in the same claim recites “the read word line being coupled to the first pass-gate transistor and the third pass-gate transistor”.
Similarly, the limitation “the second pass-gate transistor and the fourth pass-gate transistor are turned on in response to the read word line signal” is unclear because an antecedent limitation in the same claim recites “a write word line”, “being coupled to the second pass-gate transistor and the fourth pass-gate transistor”.
It appears these claims are directed toward Fig. 2A of the instant application. There is no indication in applicant’s disclosure that the write word line and the read word line are anything but electrically distinct signals, therefore it is not possible that both sets of limitations are simultaneously valid because the claimed function (turning on) cannot be realized with the claimed connectivity.
For purposes of compact prosecution (see MPEP 2173.06), the limitation regarding turning on the first and third pass-gate transistors will be interpreted as the read word line signal (RWWL), and the limitation regarding turning on the second and fourth pass-gate transistors will be interpreted to mean the write word line signal (WWL) as indicated in Fig. 2A of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1-2, 7, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. ("Implementation of High Performance SRAM Cell Using Transmission Gate"; “Sharma”) in view of Mizutani et al. (US 20220399358; “Mizutani”)
Regarding independent claim 1, notwithstanding the indefiniteness rejection above, Sharma discloses a memory cell, comprising:
a first transmission pass-gate comprising:
a first pass-gate transistor of a first type (Fig. 1);
and a second pass-gate transistor of a second type different from the first type (Fig.1),
and the second pass-gate transistor being below the first pass-gate transistor (Fig. 1. It is noted that the instant application declares that the spatially relative term "below" be defined “to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures (para. 20)) (emphasis added);
a second transmission pass-gate comprising:
a third pass-gate transistor of the first type (Fig. 1);
and a fourth pass-gate transistor of the second type (Fig. 1),
the fourth pass-gate transistor being below the third pass-gate transistor (Fig. 1);
and the read word line being coupled to the first pass-gate transistor and the third pass-gate transistor (Fig. 1 where it illustrates interconnect line WL coupled to the first and third transistors),
and being configured to receive a read word line signal;
(and a write word line…) being coupled to the second pass-gate transistor and the fourth pass-gate transistor, being configured to receive a write word line signal (Fig. 1 where it illustrates interconnect line WLB coupled to the second and forth transistors),
wherein the first pass-gate transistor and the third pass-gate transistor are turned on in response to the write word line signal during a write operation (Fig. 1 where it illustrates that interconnect line WL would turn on the two NFET transistors 1 and 3 when it is a logic 1. As noted in the indefiniteness rejection above, this element is interpreted to refer to the read word line (RWWL) in the instant application as it appears this limitation is directed to Fig. 2A of the instant application);
and the second pass-gate transistor and the fourth pass-gate transistor are turned on in response to the read word line signal during the write operation after the first pass-gate transistor and the third pass-gate transistor are turned on (Fig. 1 where it illustrates that interconnect line WLB would turn on the two PFET transistors 2 and 4 when it is a logic 0. As noted in the indefiniteness rejection above, this element is interpreted to refer to the write word line (WWL) in the instant application. Additionally, Sharma's structure is identical to that of the instant application. And as per MPEP 2114(II), in an apparatus claim, the manner of operating a device does not differentiate from the prior art. The limitation in this claim regarding the timing of turning on the transistors is directed to the manner of operating the SRAM memory cell and does not include any further apparatus limitations to distinguish the claimed apparatus from Sharma’s apparatus, nor are any means which would control the timing of the word line signals explicitly disclosed. Thus, it does not differentiate from Sharma. It is suggested that any “manner of operating” limitations be redrafted in method form.)
Sharma is silent with regard to the physical layout of the memory cell.
However, Mizutani teaches a read word line extending in a first direction, being on a first metal layer above a front-side of a substrate (Fig. 9: 980. See also para. 116; "The memory-side metal interconnect structures 980 may comprise various metal via structures and various metal line structures"),
and a write word line extending in the first direction, being on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate (Fig. 10: 918 where it illustrates backside metal interconnect. See also para. 155; "The backside metal interconnect structures 918 provide electrical connection between the layer contact via structures 86 and the backside peripheral circuit 920"),
and being separated from the read word line in a second direction different from the first direction (Fig. 20 where it illustrates frontside and backside interconnect lines),
Sharma and Mizutani are from the same field of endeavor as applicant’s invention directed to memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharma’s circuit topology with the teachings of Mizutani’s physical layout to utilize both frontside and backside connectivity. Doing so would result in a denser implementation making the memory array smaller.
Regarding claim 2, Sharma and Mizutani combined disclose the limitations of claim 1.
As applied, Sharma further discloses further comprising
a first inverter coupled to the first pass-gate transistor, the second pass-gate transistor, the third pass-gate transistor and the fourth pass-gate transistor (Fig. 1);
and a second inverter coupled to the first pass-gate transistor, the second pass-gate transistor, the third pass-gate transistor and the fourth pass-gate transistor (Fig. 1).
Regarding claim 7 and 12, Sharma and Mizutani combined disclose the limitations of claims 1 and 11 respectively.
As applied, Sharma further discloses wherein the first pass-gate transistor comprises:
a first gate extending in the second direction and being on a first level (Fig. 1);
the second pass-gate transistor comprises:
a second gate extending in the second direction, and being on a second level below the first level (Fig. 1. It is noted that the instant application defines the term "below" only as it relates to positional relationship as illustrated in the figures (para. 20), therefore this limitation is understood using the broadest reasonable interpretation to mean that second direction is “up and down on the page” and the second gate is below the first gate as illustrated in Fig. 1)
the third pass-gate transistor comprises:
a third gate extending in the second direction, being separated from the first gate in the second direction, and being on the first level (Fig. 1);
and the fourth pass-gate transistor comprises:
a fourth gate extending in the second direction, being separated from the second gate in the second direction, and being on the second level (Fig. 1. Id and for the same reasons as above).
Regarding independent claim 11, Sharma discloses a memory cell, comprising
a first transmission pass-gate comprising:
a first pass-gate transistor of a first type (Fig. 1);
and a second pass-gate transistor of a second type different from the first type, and the second pass-gate transistor being below the first pass-gate transistor (Fig. 1);
a second transmission pass-gate comprising:
a third pass-gate transistor of the first type (Fig. 1);
and a fourth pass-gate transistor of the second type, the fourth pass-gate transistor being below the third pass-gate transistor (Fig. 1);
wherein the first pass-gate transistor and the third pass-gate transistor are turned on at a first time in response to the write word line signal during a write operation; (Fig. 1 where it illustrates that interconnect line WL would turn on the two NFET transistors 1 and 3 when it is a logic 1. It appears this limitation is directed to Fig. 2B of the instant application.)
and the second pass-gate transistor and the fourth pass-gate transistor are turned on at a second time in response to the read word line signal during the write operation, (Fig. 1 where it illustrates that interconnect line WLB would turn on the two PFET transistors 2 and 4 when it is a logic 0.)
the first time being before the second time (Fig. 1. Sharma's structure is identical to that of the instant application. And as per MPEP 2114(II), in an apparatus claim, the manner of operating a device does not differentiate from the prior art. The limitation in this claim regarding the timing of turning on the transistors is directed to the manner of operating the SRAM memory cell and does not include any further apparatus limitations to distinguish the claimed apparatus from Sharma’s apparatus, nor are any means which would control the timing of the word line signals explicitly disclosed. Thus, it does not differentiate from Sharma. It is suggested that any “manner of operating” limitations be redrafted in method form).
Sharma is silent with regard to the physical layout of the memory cell.
However, Mizutani teaches a write word line extending in a first direction, being on a first metal layer above a front- side of a substrate, being coupled to the first pass-gate transistor and the third pass-gate transistor, and being configured to receive a write word line signal (Fig. 9: 980. See also para. 116; "The memory-side metal interconnect structures 980 may comprise various metal via structures and various metal line structures");
and a read word line extending in the first direction, being on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and the read word line being coupled to the second pass-gate transistor and the fourth pass-gate transistor, being configured to receive a read word line signal (Fig. 10: 918 where it illustrates backside metal interconnect. See also para. 155; "The backside metal interconnect structures 918 provide electrical connection between the layer contact via structures 86 and the backside peripheral circuit 920"),
and being separated from the write word line in a second direction different from the first direction (Fig. 20 where it illustrates frontside and backside interconnect lines),
Sharma and Mizutani are from the same field of endeavor as applicant’s invention directed to memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharma’s circuit topology with the teachings of Mizutani’s physical layout to utilize both frontside and backside connectivity. Doing so would result in a denser implementation making the memory array smaller.
Claims 3-4, 16-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. ("Implementation of High Performance SRAM Cell Using Transmission Gate"; “Sharma”) in view of Mizutani et al. (US 20220399358; “Mizutani”) and further in view of Nii et al. (US 6627960; “Nii”).
Regarding claims 3 and 16, Sharma and Mizutani disclose the limitations of claim 2 and 11 respectively.
As applied, Sharma further discloses further comprising:
(a bit line…) and being coupled to the first transmission pass-gate (Fig. 1);
(a bit line bar…) and being coupled to the second transmission pass-gate (Fig. 1);
Sharma and Mizutani combined are silent with respect to the physical layout of a bit line.
However, Nii teaches a bit line extending in the first direction, being configured to receive a bit line signal, being on the first metal layer (Fig. 19: AL17 where it illustrates the first bit line (BL11) of the cross coupled inverter SRAM cell layout being on the first metal layer),
and a bit line bar extending in the first direction, being configured to receive a bit line bar signal, being on the first metal layer (Fig. 19: AL18 where it illustrates the second bit line (BL12) of the cross coupled inverter SRAM cell layout being on the first metal layer),
Sharma and Mizutani combined as well as Nii are from the same field of endeavor as applicant’s invention directed to memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharma’s circuit topology and the teachings of Mizutani’s physical layout to utilize both frontside and backside connectivity with the teachings of Nii’s layout of a cross-coupled inverter SRAM cell. Doing so would result in a compact base memory component which could be highly replicated to form a noise tolerant SRAM array.
Regarding claims 4 and 17, Sharma, Mizutani and Nii combined disclose the limitations of claim 3 and 16 respectively.
As applied, Sharma further discloses wherein
the bit line comprises:
and being coupled to the first pass-gate transistor and the second pass-gate transistor (Fig. 1 BL);
and the bit line bar comprises:
being coupled to the third pass-gate transistor and the fourth pass-gate transistor (Fig. 1 BLB),
As applied, Nii further discloses
(the bit line comprises:) a first conductor extending in the first direction, being configured to receive the bit line signal, being on the first metal layer (Fig. 19: AL17 where it illustrates the first bit line (BL11) of the cross coupled inverter SRAM cell layout being on the first metal layer),
(and the bit line bar comprises:) a second conductor extending in the first direction, being configured to receive the bit line bar signal, being on the first metal layer (Fig. 19: AL18 where it illustrates the second bit line (BL12) of the cross coupled inverter SRAM cell layout being on the first metal layer),
and being separated from the first conductor in the second direction (Fig. 19 where it illustrates the lines AL17 and AL18 being separated by a distance in a second direction).
Regarding independent claim 21, notwithstanding the indefiniteness rejection above, Sharma discloses a memory cell, comprising:
a first transmission pass-gate comprising:
a first pass-gate transistor of a first type (Fig. 1);
and a second pass-gate transistor of a second type different from the first type (Fig.1),
and the second pass-gate transistor being below the first pass-gate transistor (Fig. 1. It is noted that the instant application defines the term "below" only as it relates to positional relationship as illustrated in the figures (para. 20));
a second transmission pass-gate comprising:
a third pass-gate transistor of the first type (Fig. 1);
and a fourth pass-gate transistor of the second type (Fig. 1),
the fourth pass-gate transistor being below the third pass-gate transistor (Fig. 1);
and the read word line being coupled to the first pass-gate transistor and the third pass-gate transistor (Fig. 1 where it illustrates interconnect line WL coupled to the first and third transistors),
(a write word line…) being coupled to the second pass-gate transistor and the fourth pass-gate transistor (Fig. 1 where it illustrates interconnect line WLB coupled to the second and forth transistors),
(a bit line…) and being coupled to the first transmission pass-gate; (Fig. 1)
(a bit line bar…) and being coupled to the second transmission pass-gate (Fig. 1);
wherein the first pass-gate transistor and the third pass-gate transistor are turned on in response to the write word line signal during a write operation (Fig. 1 where it illustrates that interconnect line WL would turn on the two NFET transistors 1 and 3 when it is a logic 1. As noted in the indefiniteness rejection above, this element is interpreted to refer to the read word line (RWWL) in the instant application as it appears this limitation is directed to Fig. 2A of the instant application);
and the second pass-gate transistor and the fourth pass-gate transistor are turned on in response to the read word line signal during the write operation after the first pass-gate transistor and the third pass-gate transistor are turned on (Fig. 1 where it illustrates that interconnect line WLB would turn on the two PFET transistors 2 and 4 when it is a logic 0. As noted in the indefiniteness rejection above, this element is interpreted to refer to the write word line (WWL) in the instant application. Additionally, Sharma's structure is identical to that of the instant application. And as per MPEP 2114(II), in an apparatus claim, the manner of operating a device does not differentiate from the prior art. The limitation in this claim regarding the timing of turning on the transistors is directed to the manner of operating the SRAM memory cell and does not include any further apparatus limitations to distinguish the claimed apparatus from Sharma’s apparatus, nor are any means which would control the timing of the word line signals explicitly disclosed. Thus, it does not differentiate from Sharma. It is suggested that any “manner of operating” limitations be redrafted in method form.)
Sharma is silent with regard to the physical layout of the memory cell.
However, Mizutani teaches a read word line extending in a first direction, being on a first metal layer above a front-side of a substrate (Fig. 9: 980. See also para. 116; "The memory-side metal interconnect structures 980 may comprise various metal via structures and various metal line structures"),
and being configured to receive a read word line signal;
a write word line extending in the first direction, being on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate (Fig. 10: 918 where it illustrates backside metal interconnect. See also para. 155; "The backside metal interconnect structures 918 provide electrical connection between the layer contact via structures 86 and the backside peripheral circuit 920"),
being configured to receive a write word line signal,
and being separated from the read word line in a second direction different from the first direction (Fig. 20 where it illustrates frontside and backside interconnect lines being separated by a distance);
Sharma and Mizutani combined are silent with respect to the physical layout of a bit line.
However, Nii teaches a bit line extending in the first direction, being configured to receive a bit line signal, being on the first metal layer (Fig. 19: AL17 where it illustrates the first bit line (BL11) of the cross coupled inverter SRAM cell layout being on the first metal layer),
and a bit line bar extending in the first direction, being configured to receive a bit line bar signal, being on the first metal layer (Fig. 19: AL18 where it illustrates the second bit line (BL12) of the cross coupled inverter SRAM cell layout being on the first metal layer),
Sharma and Mizutani combined as well as Nii are from the same field of endeavor as applicant’s invention directed to memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharma’s circuit topology and the teachings of Mizutani’s physical layout to utilize both frontside and backside connectivity with the teachings of Nii’s layout of a cross-coupled inverter SRAM cell. Doing so would result in a compact base memory component which could be highly replicated to form a noise tolerant SRAM array.
Claims 8-10 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. ("Implementation of High Performance SRAM Cell Using Transmission Gate"; “Sharma”) in view of Mizutani et al. (US 20220399358; “Mizutani”) and further in view of Nebesnyi (US 9514264)
Regarding claims 8 and 13, Sharma and Mizutani combined disclose the limitations memory of claims 7 and 12 respectively.
Sharma and Mizutani are silent with respect to explicit gate isolation in the physical layout.
However, Nebesnyi teaches further comprising:
a first gate isolation layer between the first gate and the second gate; and a second gate isolation layer between the third gate and the fourth gate (Fig. 1B where it illustrates a first gate (176), and a second gate (186) separated by a distance. It is well known in the art that there is a dielectric layer between polysilicon gates).
Sharma and Mizutani combined as well as Nebesnyi are from the same field of endeavor as applicant’s invention directed to integrated circuits useful in memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharma’s circuit topology and the teachings of Mizutani’s physical layout to utilize both frontside and backside connectivity with the teachings of Nebesnyi’s layout of a transmission gate which can be used in an TG8T SRAM cell. Doing so would result in a compact base memory component which could be highly replicated to form a noise tolerant SRAM array.
Regarding claims 9 and 14, Sharma, Mizutani and Nebesnyi combined disclose the limitations memory of claims 8 and 13 respectively.
As applied, Nebesnyi further discloses wherein the read word line comprises:
a first conductor extending in the first direction, being coupled to the first pass-gate transistor, being on the first metal layer, and overlapping the first gate (Fig. 1B where it illustrates the first gate (176) of the first pass-gate transistor, which has a contact to a metal 1 stub (first conductor) overlapping the first gate. See also col.6, ln. 41-45; "The poly gate pattern 176 is coupled (e.g., through a contact, a metal 1 stub", "to the metal line 174a", "which forms a portion of the control terminal 102 and carries the corresponding control signal." It is noted that control terminal 102 is analogous to the RWWL signal of the instant application);
and a second conductor extending in the first direction, being coupled to the third pass-gate transistor, being on the first metal layer, being separated from the first conductor in the second direction, and overlapping the third gate (Fig. 1B, third gate (196) with the same reasoning as above);
and the write word line comprises:
a third conductor extending in the first direction, being coupled to the second pass-gate transistor, being on the second metal layer, and being overlapped by the second gate (Fig. 1B where it illustrates the second gate (186, section 122) of the second pass-gate transistor which is coupled to the metal 2 line (104) which overlaps the second gate. See also col. 6, ln. 55-60; "The poly gate pattern 186 is coupled (e.g., through a contact, a metal 1 stub, and a via between metal 1 and metal 2 layers) to the metal line 188a (e.g., at metal 2 layer), which forms at least a portion of the control terminal 104 and carries the corresponding control signal." It is noted that control terminal 104 is analogous to the WWL signal of the instant application);
and a fourth conductor extending in the first direction, being coupled to the fourth pass-gate transistor, being on the second metal layer, being separated from the third conductor in the second direction, and being overlapped by the fourth gate (Fig. 1B, fourth gate (186, section 132) with the same reasoning as above).
Regarding claims 10 and 15, Sharma, Mizutani and Nebesnyi combined disclose the limitations memory of claims 9 and 14 respectively.
As applied, Nebesnyi further discloses further comprising:
a first via electrically coupling the first conductor and the first gate together, the first via being between the first conductor and the first gate (Fig. 1B, the via between control line (102) and the first gate (176));
a second via electrically coupling the third conductor and the second gate together, the second via being between the third conductor and the second gate (Fig. 1B, the via between control line (102) and the second gate (196));
a third via electrically coupling the second conductor and the third gate together, the third via being between the second conductor and the third gate (Fig. 1B, the via between control line (104) and the third gate (186, section 122));
and a fourth via electrically coupling the fourth conductor and the fourth gate together, the fourth via being between the fourth conductor and the fourth gate (Fig. 1B, the via between control line 104 and the fourth gate (186, section 132). It is noted that the third and fourth via regions are effectively shared as the control line (104) is also effectively shared due to a routine design choice to combine and is electrically analogous to the instant application as the same control line is shared by the third and fourth transistors in the instant application).
Claims 5-6 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. ("Implementation of High Performance SRAM Cell Using Transmission Gate"; “Sharma”) in view of Mizutani et al. (US 20220399358; “Mizutani”) and further in view of Nii et al. (US 6627960; “Nii”) and further in view of Nebesnyi (US 9514264)
Regarding claims 5 and 18, Sharma, Mizutani and Nii combined disclose the limitations memory of claims 4 and 17 respectively.
Sharma, Mizutani and Nii are silent with respect to the explicit physical layout of the transmission gates.
However, Nebesnyi teaches further comprising:
a first contact extending in the second direction (Fig. 1B. See also col. 6, ln. 61-62; "In the layout of the transmission gate 150 in FIG. 1B, one pair of diffusion terminals 116 and 126 of the FETs 110 and 120 (of the transmission gate in Fig. 1A), respectively, are coupled through a connection 180, for example, at the metal 1 layer. It is well known in the art that a contact is used to connect metal 1 to diffusion"),
and being electrically coupled to a source/drain of the first pass-gate transistor and a source/drain of the second pass-gate transistor (Fig. 1 where it shows the signal QB connected to the drain/source of the first and second pass-gate transistors);
and a second contact extending in the second direction (Fig. 1B. See also col. 7, ln. 36-39; "In the layout of the transmission gate 160 in FIG. 1B, one pair of diffusion terminals 136 and 146 of the FETs 130 and 140, respectively, are coupled through a connection 192 for example, at the metal 1 layer. It is well known in the art that a contact is used to connect metal 1 to diffusion"),
and being electrically coupled to a source/drain of the third pass-gate transistor and a source/drain of the fourth pass-gate transistor (Fig. 1 where it shows the signal Q connected to the drain/source of the third and second pass-gate transistors),
and being separated from the first contact in at least the first direction or the second direction (Fig. 1B where it shows the contacts for line 180 and 192 being separated by a distance).
Sharma, Mizutani and Nii combined as well as Nebesnyi are from the same field of endeavor as applicant’s invention directed to integrated circuits useful in memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharma’s circuit topology and the teachings of Mizutani’s physical layout to utilize both frontside and backside connectivity with the teachings of Nii’s layout of a cross-coupled inverter SRAM cell with Nebesnyi’s layout of a transmission gate which can all be used in an TG8T SRAM cell. Doing so would result in a compact base memory component which could be highly replicated to form a noise tolerant SRAM array.
Regarding claims 6 and 19, Sharma, Mizutani and Nii combined disclose the limitations memory of claims 5 and 18 respectively.
Sharma, Mizutani and Nii are silent with respect to the explicit physical layout of the transmission gates.
However, Nebesnyi teaches further comprising:
a first via electrically coupling the first conductor and the first contact together (Fig. 1B where it illustrates vias connecting to metal 2 and contacts to diffusion. It is noted that the term "contact" is defined in the instant application as a "metal over diffusion" layer for which a contact cut region to diffusion is created. This structure is apparently directed to the bit line or bit line bar input to the transmission gates of Fig. 2A of the instant application. It is noted that while Nebesnyi's layout diagram does not explicitly indicate connection of the transmission gate input above metal 1for sake of brevity, doing so would merely be a routine design choice),
the first via being between the first conductor and the first contact (Fig. 1B where it illustrates vias connecting to metal 2 and contacts to diffusion. It is well understood in the art that the via layer connects metal 2 to the poly or metal 1 layer);
and a second via electrically coupling the second conductor and the second contact together, the second via being between the second conductor and the second contact (Id and for the same reason).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Doluca et al. (US 11170844) - TG8T SRAM cell w/RDL & WRL
Zeng et al. (US 20090026619) - backside metal
Su et al. (US 20220352256) - backside mem cell bit lines (TSMC)
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/James S Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825