DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 102 (A1) as being anticipated by Marimuthu et al. (US 2019/0088603 A1).
Regarding Claim 1, Marimuthu (Fig. 14a) discloses a semiconductor device, comprising:
an electrical component (124);
a first interconnect structure (600, 716) disposed adjacent to the electrical component (124);
a split antenna structure (antennae 734 left and core substrate 732 left; antennae 734 right and core substrate 732 right) disposed over the electrical component (124) and first interconnect structure (600, 716 left and right) (“the upper PCB unit does not physically contact the semiconductor die even though some vertical overlap exists” [0105])
and including;
(a) a first antenna section (section around 734 left) with a first substrate (732 left) and a first antenna (734 left) disposed over the first substrate (600, 716 left and right), and
(b) a second antenna section (section around antennae 734 right) with a second substrate (732 right) and a second antenna (antennae 734 right) disposed over the second substrate (732 right), wherein
the first antenna section (section around antennae 734 left) is physically separated by a gap (802) from the second antenna section (section around antennae 734 right); and
a second interconnect structure (746, 646) formed over the electrical component (124) and first interconnect structure (600, 716).
The Examiner notes that limitation “a split antenna structure disposed over the electrical component and first interconnect structure” and “a second interconnect structure formed over the electrical component and first interconnect structure” is considered to be met as long as long as a split antenna structure and second interconnect structure is disposed on a level above/below the electrical component and first interconnect structure. The Examiner notes that claim does not require “directly over”.
Regarding Claim 2, Marimuthu discloses the semiconductor device of claim 1, wherein
further including an encapsulant (an encapsulant 750) deposited between the first substrate (732 left) and second substrate (732 right).
Regarding Claim 3, Marimuthu discloses the semiconductor device of claim 1, further including
an adhesive material (742) disposed between the first antenna section (section around 734 left) and second antenna section (section around 734 right).
Regarding Claim 4, Marimuthu discloses the semiconductor device of claim 1, wherein the first interconnect structure (600, 716) includes an interposer unit (core substrate 600).
Regarding Claim 5, Marimuthu discloses the semiconductor device of claim 4, wherein
the first interconnect structure (600, 716) includes a conductive via (716) formed within the interposer unit (600).
Regarding Claim 6, Marimuthu discloses the semiconductor device of claim 1, further including
an encapsulant (750) deposited around the electrical component (124) and first interconnect structure (600, 716).
Regarding Claim 7, Marimuthu (Fig. 14a) discloses the semiconductor device, comprising:
an electrical component (124);
a first interconnect structure (600, 716); and
a split antenna structure (734 left and 732 left; 734 right and 732 right) disposed over the electrical component (124) (“the upper PCB unit does not physically contact the semiconductor die even though some vertical overlap exists” [0105]) and first interconnect structure (734 left and 732 left) with a first antenna section (section around 734 left and 732 left) of the split antenna structure (734 left and 732 left; 734 right and 732 right) separated from a second antenna section (section around 734 right and 732 right) of the split antenna structure. (734 left and 732 left; 734 right and 732 right).
The Examiner notes that limitation “a split antenna structure disposed over the electrical component and first interconnect structure” is considered to be met as long as long as a split antenna structure is disposed on a level above the electrical component and first interconnect structure. The Examiner notes that claim does not require “directly over”.
Regarding Claim 8, Marimuthu discloses the semiconductor device of claim 7, further including
a second interconnect structure (746, 646) formed over the electrical component (124) and first interconnect structure (600).
Regarding Claim 9, Marimuthu discloses the semiconductor device of claim 7, wherein
the first antenna section (734 left and 732 left) includes a first substrate (732 left) and a first antenna (734 left) disposed over the first substrate (732 left) and the second antenna section (734 right and 732 right) includes a second substrate (732 right) and a second antenna (734 right) disposed over the second substrate (732 right) with separation (802) between the first substrate (732 left) and second substrate. (732 right). (See annotated Fig. 14a)
Regarding Claim 10, Marimuthu (Fig. 14) discloses the semiconductor device of claim 7, further including an adhesive material (742, 750) disposed between the first antenna section (section around 734 left and 732 left) and second antenna section (section around 734 right and 732 right).
Regarding Claim 11, Marimuthu (Fig. 14) discloses the semiconductor device of claim 7, wherein
the first interconnect structure (600, 716) includes an interposer unit (core substrate 600).
Regarding Claim 12, Marimuthu (Fig. 14) discloses the semiconductor device of claim 11, wherein
the first interconnect structure (600, 716) includes a conductive via (716) formed within the interposer unit (600).
Regarding Claim 13, Marimuthu (Fig. 14) discloses the semiconductor device of claim 7, further including
an encapsulant (750) deposited around the electrical component (124) and first interconnect structure (600, 716).
Response to Arguments
Applicant’s arguments, see pages 9-10, filed 03/20/2026, with respect to the rejection(s) of claim(s) 1 and 7 under rejected under 35 U.S.C. 102 (A1) as being anticipated by embodiment of Fig. 12 of Marimuthu et al. (US 2019/0088603 A1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under rejected under 35 U.S.C. 102 (A1) as being anticipated by embodiment of Fig. 14 of Marimuthu et al. (US 2019/0088603 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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