Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of group I, claims 1-10 and 21-30, in the reply filed on 04/13/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites “wherein the first lower transistor is not part of active circuitry and the first gate, the first source/drain region”, whereas in claim 1, it is stated that “forming a first lower transistor comprising a first gate and a first source/drain region.” This limitation is ambiguous, it is not clear what exactly forms the first lower transistor, and how it is positioned in relation to the active circuitry. Furthermore, claim 7 states “the second conductive feature are all coupled to a power supply voltage VDD”. This limitation is ambiguous as well since claim 1 says “a second conductive feature in a substrate”. The plurality of the second conductive has not been stated anywhere, there is inconsistency between the two related limitations. For the purposes of the art rejection below this claim has been interpreted to be “the first lower transistor, and the second conductive feature are coupled to a power supply voltage VDD.”
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10, 26-28 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. (Pub. No. US 2010/0012997 A1, herein Jang).
Regarding claim 1, Jang discloses a method comprising: forming a first conductive feature 102 ([0038]) and a second conductive feature 104 ([0038]) in a substrate 100 ([0038]); forming a first complementary Field-Effect Transistor (CFET) over the substrate ([0002]), the forming comprising: forming a first lower transistor comprising a first gate 120 ([0040]) and a first source/drain region 110S/D ([0043]); and forming a first upper transistor comprising a second gate 220 ([0046]) and a second source/drain region 210S/D ([0048]), the first upper transistor overlapping the first lower transistor (Figs. 3B, 4B, 5B); and forming a conductive via fuse 401 connected (is taken to mean electrically and/or physically connected) to the first conductive feature and the second source/drain region (Figs. 8A-8C, [0053]).
Regarding claim 2, Jang discloses the method of claim 1, wherein the conductive via fuse is adjacent the first lower transistor (In Fig. 3B of Jang, the conductive via 301 is adjacent the first lower gate 120 which is part of the first lower transistor.).
Regarding claim 3, Jang inherently discloses the method of claim 1, wherein the first and second conductive features are buried power rails ([0006], [0017], In memory devices, buried power rails are power distribution lines typically VDD and VSS, that are placed below the active transistor layer, inside or near silicon substrate.).
Regarding claim 4, Jang inherently discloses the method of claim 1, wherein the first conductive feature is a bit line of a memory cell array ([0028], [0036]).
Regarding claim 5, Jang discloses the method of claim 1 further comprising: forming a conductive via 301 connected (is taken to mean electrically and/or physically connected) to the second conductive feature 104 and the first source/drain region 110S/D ([0053], [0055]).
Regarding claim 6, Jang discloses the method of claim 5, wherein the conductive via fuse 401 is longer than the conductive via 301 (Figs. 3B, 4B, 5B and [0052]-[0053]).
Regarding claim 7, Jang discloses the method of claim 5, wherein the first lower transistor is not part of active circuitry and the first gate, the first source/drain region, and the second conductive feature are all coupled to a power supply voltage VDD ([0006], [0017], In memory devices, buried power rails are power distribution lines typically VDD and VSS, that are placed below the active transistor layer, inside or near silicon substrate.).
Regarding claim 8, Jang discloses the method of claim 1, wherein the conductive via fuse is configured to function as a fuse for the CFET (Figs. 3B, 4B, 5B and [0052]-[0053]).
Regarding claim 9, Jang discloses the method of claim 1, wherein the first lower transistor and the first upper transistor are formed by processes comprising: forming the first lower transistor in a first wafer; forming the first upper transistor in a second wafer; and bonding the first wafer to the second wafer (Figs. 3B, 4B, 5B and [0085], [0100]).
Regarding claim 10, Jang discloses the method of claim 1, wherein the first upper transistor is formed after the first lower transistor has been formed (Figs. 3B, 4B, 5B and [0085], [0100]).
Regarding claim 26, Jang discloses a method comprising: forming a conductive feature 102/104 ([0038) in a substrate 100 ([0038]); forming a lower transistor over the substrate, the lower transistor comprising a first source/drain region 110S/D ([0043]); forming an interlayer dielectric 140 ([0044]) over the first source/drain region; forming a bond layer 200 ([0045]) over the interlayer dielectric; forming an upper transistor over the bond layer, the upper transistor comprising a second source/drain region 210S/D ([0048]), the upper transistor overlapping the lower transistor (Figs. 3B, 4B, 5B); and forming a conductive via fuse 401 ([0053]) extending through the bond layer and the interlayer dielectric (Figs. 3B, 4B, 5B), the conductive via fuse connecting the second source/drain region and the conductive feature (8A-8C, [0053]).
Regarding claim 27, Jang inherently discloses the method of claim 26, wherein the lower transistor and the upper transistor form a complementary field-effect transistor (CFET) (Figs. 3B, 4B, 5B and [0002]).
Regarding claim 28, Jang inherently discloses the method of claim 26, further comprising: programming the conductive via fuse by causing electromigration in the conductive via fuse ([0003], [0022], [0030], In the memory device, programming is performed by driving a controlled current through a conductive via, causing electromigration of metal atoms within the via. The resulting structural change, such as formation or disruption of a conductive path, alters the via’s resistance and thereby stores the programmed data state.).
Regarding claim 30, Jang inherently discloses the method of claim 26, wherein the conductive via fuse is in a memory cell area ([0003], [0022], [0030]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Fulford et al. (Pub. No. US 2021/0351180 A1, herein Fulford).
Regarding claim 29, Jang does not specifically disclose wherein the lower transistor comprises first semiconductor nanostructures as channel regions and the upper transistor comprises second semiconductor nanostructures as channel regions.
However, in the same field of endeavor, Fulford teaches a method of making multiple nano layer transistors, wherein the lower transistor with bottom S/D regions 130-138 ([0054]) comprises first semiconductor nanostructures as channel regions 114/116 ([0053]-[0054]) and the upper transistor with top S/D regions 126-128 ([0054]) comprises second semiconductor nanostructures as channel regions 110/112 ([0044], [0051]) to enhance a multiple stack CFET performance by improving the mobility and thus increasing the on current, which can also help to control the short channel effect ([0002]).
Therefore, given the teachings of Fulford, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Jang in view of Fulford by employing the nanostructures as channel regions.
Allowable Subject Matter
Claims 21-25 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 21, Jang discloses a method comprising: forming a first conductive feature 102 ([0038]) and a second conductive feature 104 ([0038]) in a substrate 100 ([0038]); forming a first complementary Field-Effect Transistor (CFET) over the substrate ([0002]), the forming comprising: forming a first lower transistor comprising a first gate 120 ([0040]) and a first source/drain region 110S/D ([0043]); and forming a first upper transistor comprising a second gate 220 ([0046]) and a second source/drain region 210S/D ([0048]), the first upper transistor overlapping the first lower transistor (Figs. 3B, 4B, 5B); and forming a conductive via fuse 401 connected (is taken to mean electrically and/or physically connected) to the first conductive feature and the second source/drain region (Figs. 8A-8C, [0053]). Jang alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, forming a first contact structure on and connected to the first source/drain region; forming a first conductive via connecting the first contact structure and the first buried conductive feature; forming a second contact structure on and connected to the second source/drain region; and forming a second conductive via connecting the second contact structure and the second buried conductive feature. Claims 22-25 are included likewise as they depend from claim 21.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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May 6, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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