DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Application
In response to Office action dated 02/11/2026 (“02-11-26 OA”), Applicant filed remarks and currently amended title and claims 1, 3, 5-7 and 9 while currently canceling claims 4, 13 and 18-20 in reply dated 05/11/2026 (“05-11-26 Reply”).
Response to Arguments
Applicant’s amendments to title overcome the objection to specification as set forth under line item number 1 of the 02-11-26 OA.
Applicant’s amendments to independent claim 1 have overcome the prior art rejections based at least in part on Hsieh as set forth under line item number 2 of the 02-11-26 OA.
Applicant’s amendments to independent claim 1 have overcome the prior art rejections based at least in part on Chung as set forth under line item numbers 3-4 of the 02-11-26 OA.
Neither Hsieh nor Chung nor Muller teach the newly added limitation in independent claim 1 reciting, “wherein the spacer is further located on and contacts a sidewall of the variable resistance layer.” Further, “contact” means touching.
Amendments to independent claim 1 changed the scope of claim 1 and dependent claims thereof, thereby necessitating a new grounds of rejection infra.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0194668 A1 to Sato.
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Regarding independent claim 1, Sato teaches of a resistive memory structure (as defined below), comprising:
a transistor device (see title: “transistor cell”) comprising:
a substrate (see Figure 7 and paragraph 0044: “he body region 710, the source region 732, and the drain region 734 can be located within a semiconductor material layer (which may be a semiconductor substrate or may be located in an upper portion of a substrate”);
a gate 756 (“gate electrode”; Figure 2; see abstract, paragraphs 0041-0042, 0045, 0048) over the substrate 710;
a gate dielectric layer 752 (“gate dielectric”; Figure 2, paragraph 0045) located between the gate 756 and the substrate 710;
a first doped region 732 (“source region”; Figure 2; paragraph 0044) and a second doped region 734 (“drain region”; Figure 2; paragraph 0044) located in the substrate 710 on two sides of the gate 756; and
a spacer 755 (“dielectric gate spacer”; Figure 2; paragraph 0048) located on a sidewall of the gate 756 and a sidewall (see Figure 2) of the gate dielectric layer 752; and
a resistive memory device (see title: “INTERFACIAL RESISTIVE MEMORY GATE STACK TRANSISTOR CELL AND METHODS OF MANUFACTURING THE SAME”) electrically connected to the gate 756 of the transistor device (as defined supra) and comprising a variable resistance layer 754 (“resistive memory material layer”; Figure 2; paragraph 0048), wherein the spacer 754 is further located on and contacts (see Figure 2) a sidewall of the variable resistance layer 754.
Regarding claim 2, Sato teaches wherein the transistor device (as defined in claim 1 rejection supra) and the resistive memory device (as defined in claim 1 rejection supra) share (see Figure 2: shared gate 756) the gate 754.
Regarding claim 3, Sato teaches the transistor device (as defined in claim 1 rejection supra) is located on the substrate 710, and the resistive memory device (as defined in claim 1 rejection supra) is located on (see Figure 2: 654 is literally on the transistor: source/drain/gate) the transistor device (as defined in claim 1 rejection supra).
Regarding claim 5, Sato teaches wherein the gate dielectric layer 752 comprises a single-layer structure (see paragraph 0045: “The gate dielectric 752 includes at least one dielectric material layer such as a silicon oxide layer, a dielectric metal oxide layer, or a stack thereof”).
Regarding claim 6, Sato teaches wherein the gate dielectric layer 752 comprises a multilayer structure (see paragraph 0045: “The gate dielectric 752 includes at least one dielectric material layer such as a silicon oxide layer, a dielectric metal oxide layer, or a stack thereof”).
Regarding claim 7, Sato teaches wherein the gate dielectric layer 752 comprises:
a first dielectric layer 752 (refer to claims 5-6 rejection supra: given the order listed there may be SiO and metal oxide stacked) located between the gate 756 and the substrate 710; and a second dielectric layer (refer to claims 5-6 rejection supra: given the order listed there may be SiO and metal oxide stacked) located between the gate 756 and the first dielectric layer 752.
Regarding claim 8, Sato teaches wherein a material of the first dielectric layer comprises silicon oxide, and a material of the second dielectric layer comprises a high dielectric constant material (refer to claim 7 rejection supra).
Allowable Subject Matter
Claims 9-12 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 contains allowable subject matter, because the closest art of record, singularly of in combination, fails to disclose or suggest, in combination with the other elements of claim 9, wherein the resistive memory device comprises: the gate; an electrode located on the gate; and the variable resistance layer located between the electrode and the gate.
Dependent claims 10-12 and 14-17 contain allowable subject matter, because they depend on the allowable subject matter of claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as listed on the current Notice of References Cited-892 Form: Reference B depicts curved U-shaped bottom electrode and variable resistance layers
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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27 June 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
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