DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
No claim to an application for domestic benefit.
Foreign Priority
Receipt is acknowledged of certified copies of papers (i.e., application number 112139635 filed in Taiwan on 10/17/2023) required by 37 CFR 1.55, received 12/11/2023.
Information Disclosure Statement
Currently, no information disclosure statement filed.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
--RESISTIVE MEMORY STRUCTURE INTEGRATED WITH A TRANSISTOR GATE--.
Prior art rejections based on primary reference Hsieh.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by journal article entitled A three-bit-per-cell via-type resistive random access memory gated metal-oxide semiconductor field-effect transistor non-volatile memory with the FORMing-free characteristic by Hsieh et al. (“Hsieh”).
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Regarding independent claim 1, Hsieh teaches of a resistive memory structure (refer to title), comprising:
a transistor device (see Figure 1b: Mosfet) comprising a gate (see Figure 1b: Poly-gate); and
a resistive memory device (see Figure 1b: RRAM; also see Figure 1a) electrically connected (see Figure 1b: Via and Metal) to the gate (see Figure 1b: Poly-gate) of the transistor device (see Figure 1b: Mosfet).
Regarding claim 18, Hsieh teaches wherein the resistive memory device (refer to title) comprises:
a first electrode (see Figure 1b with Figure 1a: bottom electrode) located on the gate (see Figure 1b: Poly-gate) and electrically connected (see Figure 1b: Via) to the gate (see Figure 1b: Poly-gate);
a second electrode (see Figure 1b with Figure 1a: top electrode) located on the first electrode (see Figure 1b with Figure 1a: bottom electrode); and
a variable resistance layer (see Figure 1b with Figure 1a: HfO2) located between the second electrode (see Figure 1b with Figure 1a: top electrode) and the first electrode (see Figure 1b with Figure 1a: bottom electrode).
Regarding claim 19, Hsieh teaches of an interconnect structure (see Figure 1b: Via) located between the first electrode (see Figure 1b with Figure 1a: bottom electrode) and the gate (see Figure 1b: Poly-gate) and electrically connected (see Figure 1b: electrically connected by Metal and Silicide) to the first electrode (see Figure 1b with Figure 1a: bottom electrode) and the gate (see Figure 1b: Poly-gate).
Regarding claim 20, Hsieh teaches wherein a material of the variable resistance layer comprises metal oxide (see Figure 1b with Figure 1a: HfO2).
Prior art rejections based on primary reference Chung.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9-11, 14-15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2016/0027507 A1 to Chung et al. (“Chung”).
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Regarding independent claim 1, Chung teaches of a resistive memory structure (see title), comprising:
a transistor device 124 (see Figures 6-7: field effect transistor; paragraph 0032) comprising a gate G (see Figures 6-7: gate terminal; paragraph 0032); and
a resistive memory device 122 (see Figures 6-7: storage unit; paragraphs 0032) electrically connected (see Figures 6-7: part of 122 is shared by 124, specifically the gate is the bottom electrode: “G/BE”) to the gate G of the transistor device 124.
Regarding claim 2, Chung teaches in Figures 6-7 wherein the transistor device 124 and the resistive memory device 122 share the gate BE/G.
Regarding claim 3, Chung teaches in Figure 7 of a substrate (see Examiner’s Annotated Figure 7 of Chung, supra), wherein
the transistor device 124 is located on the substrate (see Examiner’s Annotated Figure 7 of Chung, supra), and
the resistive memory device 122 is located on (see Figure 7) the transistor device 124.
Regarding claim 4, Chung teaches wherein the transistor device 124 further comprises:
a gate dielectric layer (Figure 7, paragraph 0038: there is a gate dielectric between G and the substrate) located between the gate G and the substrate (labeled in Examiner’s Annotated Figure 7, supra);
a first doped region S and a second doped region D located in the substrate (labeled in Examiner’s Annotated Figure 7, supra) on two sides (i.e., left and right side) of the gate G; and
a spacer (shows in Figure 7 on the side of the gate dielectric and G) located on a sidewall of the gate G and a sidewall of the gate dielectric layer (Figure 7, paragraph 0038: there is a gate dielectric between G and the substrate).
Regarding claim 5, Chung teaches in Figure 7 with paragraph 0038 wherein the gate dielectric layer (Figure 7, paragraph 0038: there is a gate dielectric between G and the substrate) comprises a single-layer structure (see end of paragraph 0038: “at least one layer of SiO2”; therefore there is at least one embodiment of a single layer).
Regarding claim 6, Chung teaches in Figure 7 with paragraph 0038 wherein the gate dielectric layer (Figure 7, paragraph 0038: there is a gate dielectric between G and the substrate) comprises a multilayer structure (see end of paragraph 0038: “at least one layer of SiO2”; also see claim 8: “gate dielectric layers”, in the plural form; therefore there is at least one embodiment of a multilayer).
Regarding claim 7, Chung teaches in Figure 7 with paragraph 0038 and with Chung’s claim 8 wherein the gate dielectric layer Figure 7, paragraph 0038: there is a gate dielectric between G and the substrate) comprises:
a first dielectric layer (given Figure 7 and paragraph 0038 and claim 8: there does appear to be a situation where there is more than one layer, hence “at least one layer”) located between the gate G and the substrate (labeled in Examiner’s Annotated Figure 7, supra); and
a second dielectric layer (given Figure 7 and paragraph 0038 and claim 8: there does appear to be a situation where there is more than one layer, hence “at least one layer”) located between (given that there is a stack of more than one gate dielectric layer therefore the layers necessarily have one layer closer to substrate and another layer closer to the gate G) the gate G and the first dielectric layer (as explained supra).
Regarding claim 9, Chung teaches in Figure 7 wherein the resistive memory device 122 comprises:
the gate G/BE;
an electrode TE located on the gate G/BE; and
a variable resistance layer DI located between the electrode TE and the gate G/BE.
Regarding claim 10, Chung teaches wherein the electrode TE comprises a single-layer structure (see paragraph 0035: “at least one layer”; therefore TE may be a single layer in an embodiment).
Regarding claim 11, Chung teaches wherein the electrode TE comprises a multilayer structure (see paragraph 0035: “at least one layer”; therefore TE may be multilayer in an embodiment).
Regarding claim 14, Chung teaches wherein the variable resistance layer DI comprises a single-layer structure (see paragraph 0035: “at least one layer”; therefore DI may be a single layer in an embodiment).
Regarding claim 15, Chung teaches wherein the variable resistance layer DI comprises a multilayer structure (see paragraph 0035: “at least one layer”; therefore DI may be a multilayer in an embodiment).
Regarding claim 17, Chung teaches wherein a material of the variable resistance layer DI comprises metal oxide (see paragraph 0035: “noble metal-oxide compounds”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 12-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0027507 A1 to Chung et al. (“Chung”) in view of US 2019/0130957 A1 to Muller et al. (“Muller”).
Chung teaches all limitations of claim 1, 3, 4 and 7 from which claim 8 depends.
Regarding claim 8, Chung teaches of gate dielectric layers that are stacked between the gate G and the substrate. Chung teaches in claim 8 along with paragraph 0038 that the stack of dielectric layer includes low-k layers and high-k dielectric layers but does not expressly teach which layer is closer to the substrate and which layer is closer to the gate.
The problem encountered by Chung as suggested by Muller in paragraph 0119 is providing the correct material for the interface layer closest to substrate.
Muller illustrates in Figure 8E, paragraph 0119 that there is a transistor and also a memory device in 200a. The gate dielectric 122-1 closest to the substrate is a 122-1 interface layer that is silicon oxide whereas the gate dielectric 122-2 closest to the gate is a high-k material.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize that combining Muller’s gate dielectric layers with Chung’s invention would have been beneficial in order to obtain the correct/optimum conductance between the substrate and gate for the different interfaces.
Chung teaches all limitations of claims 1, 3, 4 and 9 from which each claim 12 and 13 and 16 depend.
Regarding claims 12-13 and 16, Chung teaches in paragraph 0035 that the top electrode layer TE may be more than one layer, but Chung does not teach of forming a U-shape for the top electrode layer.
The problem encountered by Chung is that of minimizing dimensions while at the same time increasing conductivity and memory storage.
Muller solves this issue as illustrated in Figure 8E, paragraph 0127 such that the top electrode 128 has u-shaped layer 128t and a filling layer of 128g. Muller also teaches that the functional layer 126 that is the functional layer for the memory device (similar to the resistive memory layer DI of Chung) is a u-shape, thereby increasing surface area and saving vertical space. Last, Muller teaches that the entirety of the memory structure including the functional layer 126 of the memory device and gates of the transistor are directly adjacent spacers 252.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize that combining Muller’s u-shaped top electrode and u-shaped memory layer all contained inside spacers with Chung’s invention would have been beneficial in order to obtain smaller horizontal dimensions while increasing conductivity and memory while shrinking the dimensions to fit within the spacer structure as taught by Muller in Figure 8E.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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31 December 2025
/John P. Dulka/Primary Examiner, Art Unit 2817