Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chow (PGPub No. 20080157318) in further view of Yu (US Patent No. 9496189) and Mahajan (PGPub No. 20150171015).
Regarding claim 1, Chow teaches a structure comprising: a first semiconductor die comprising integrated circuit regions (Fig. 2 points to substrates 108 and 110 (first semiconductor die).); second semiconductor dies disposed over and electrically connected to the first semiconductor die (Id. points to integrated circuit dies 242 and 256 (second semiconductor dies).); a bridge die disposed over and electrically connected to the first semiconductor die, the integrated circuit regions being electrically connected to each other through the bridge die (Id. points to a bridge integrated circuit package system 102.).
Chow fails to teach a dummy region, wherein the integrated circuit regions are laterally connected to each other through the dummy region; the bridge die covering the dummy region of the first semiconductor die; and a gap filling layer disposed on the first semiconductor die to laterally encapsulate the bridge die and the second semiconductor dies.
Chow in combination with Yu teaches a dummy region, wherein the integrated circuit regions are laterally connected to each other through the dummy region (Fig. 1 of Yu points to a semiconductor device 100 comprising integrated circuit dies 105 and an encapsulant 103 (dummy region).); and the bridge die covering the dummy region of the first semiconductor die (Fig. 2 of Chow points to the bridge integrated circuit package system 102.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Chow and Yu, such that a dummy region is formed between the integrated circuit regions and underneath the bridge die in order to improve physical stability by forming a single united layer that provides lateral electrical isolation between each of the integrated circuit regions.
Chow et al. still fails to teach a gap filling layer disposed on the first semiconductor die to laterally encapsulate the bridge die and the second semiconductor dies.
Mahajan teaches a gap filling layer disposed on the first semiconductor die to laterally encapsulate the bridge die and the second semiconductor dies (Figs. 3-4 and [0035] point to an integrated circuit (IC) package comprising an electrically insulating material 312 (gap fill layer) such as a molding compound.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Mahajan, such that a gap filling layer is formed to laterally encapsulate the bridge die and the second semiconductor dies in order to provide a level of electrical insulation between each of the dies.
Regarding claim 2, Chow teaches wherein the first semiconductor die comprises a first bonding structure (Fig. 2, [0045], and [0047] point to substrates 108 and 110 (first semiconductor substrate), and top surfaces 246 and 260 (first bonding structure).), each of the second semiconductor dies comprises a second bonding structure (Fig. 2, [0044], and [0048] point to circuit dies 242 and 256 (second semiconductor dies), which although shown as wire bond chips may be a different type of chip such as a flip chip. In light of this, it is considered obvious that said dies may be configured as flip chips, wherein each die further includes external connectors/bumps (second bonding structure).), the bridge die comprises a third bonding structure (Fig. 2 points to bridge interconnects 104 (third bonding structure).), the second bonding structure of each of the second semiconductor dies is in contact with and electrically connected to the first bonding structure, and the third bonding structure is in contact with and electrically connected to the first bonding structure (Id. points to the top surfaces 246 and 260 (first bonding structure), dies 242 and 256 (second semiconductor dies; second bonding structure), and bridge interconnects 104 (third bonding structure).).
Regarding claim 3, Chow teaches wherein the first semiconductor die comprises a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a first bonding structure electrically connected to the first interconnect structure (Fig. 2, [0045], and [0047] point to substrates 108 and 110 (first semiconductor substrate), top contacts 248 and 262 (first interconnect structure), and top surfaces 246 and 260 (first bonding structure).), each of the second semiconductor dies comprises a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate, and a second bonding structure disposed on and electrically connected to the second interconnect structure (Fig. 2, [0044], and [0048] point to circuit dies 242 and 256 (second semiconductor dies), which although shown as wire bond chips may be a different type of chip such as a flip chip. In light of this, it is considered obvious that said dies may be configured as flip chips, wherein each die further includes internal interconnects/pads (second interconnect structure), an underlying substrate, and external connectors/bumps (second bonding structure).), the bridge die comprises a third semiconductor substrate, a third interconnect structure disposed on the third semiconductor substrate, and a third bonding structure disposed on and electrically connected to the third interconnect structure (Fig. 2 points to the bridge integrated circuit package system 102 (bridge die) further comprising a substrate 224, a bottom surface 232 (third interconnect structure), and bridge interconnects 104 (third bonding structure).), the second bonding structure of each of the second semiconductor dies is in contact with and electrically connected to the first bonding structure, and the third bonding structure is in contact with and electrically connected to the first bonding structure (Id. points to the top surfaces 246 and 260 (first bonding structure), dies 242 and 256 (second semiconductor dies; second bonding structure), and bridge interconnects 104 (third bonding structure).).
Regarding claim 4, Chow teaches wherein the first semiconductor die further comprises conductive through vias penetrating through the first semiconductor substrate (Fig. 2 points to the substrates 108 and 110 (first semiconductor die) comprising unlabeled components (conductive through vias) extending vertically between each substrate and which appear to functionally correspond to interlayer connects 238 as seen within the bridge substrate 224), the first interconnect structure and the first bonding structure are disposed on opposite sides of the first semiconductor substrate, and the first interconnect structure is electrically connected to the first bonding structure through the conductive through vias (Id. points to the top surfaces 246 and 260 (first bonding structure) and bottom contacts 250 and 264 (first interconnect structure).).
Regarding claim 5, Chow teaches conductive terminals disposed on and electrically connected to the first interconnect structure of the first semiconductor die ([0045] and [0049] points to top contacts 248 and 262 (first interconnect structure) comprising terminal pads (conductive terminals).).
Regarding claim 6, Chow teaches wherein the first bonding structure comprises a first bonding dielectric layer and first bonding conductors embedded in the first bonding dielectric layer (Fig. 2, [0045], and [0047] point to top contacts 248 and 262 (first bonding conductors) exposed at the top surfaces 246 and 260 (first bonding structure; first bonding dielectric layer).), the second bonding structure comprises a second bonding dielectric layer and second bonding conductors embedded in the second bonding dielectric layer (Fig. 2, [0044], and [0048] point to circuit dies 242 and 256 (second semiconductor dies), which although shown as wire bond chips may be a different type of chip such as a flip chip. In light of this, it is considered obvious that said dies may be configured as flip chips, wherein each die further includes underlying connectors (second bonding conductors) that are surrounded by a protection layer such as an underfill material (second bonding dielectric layer).), the third bonding structure comprises a third bonding dielectric layer and third bonding conductors embedded in the third bonding dielectric layer (Fig. 2 points to the bridge integrated circuit package system 102 (bridge die) further comprising a bottom surface 232 (third bonding dielectric layer), and bridge bottom contacts 236 (third bonding conductors).), the first bonding conductors are bonded to the second bonding conductors and the third bonding conductors, and the second bonding dielectric layer and third bonding dielectric layer are bonded to portions of the first bonding dielectric layer (Id. points to the top surfaces 246 and 260 (first bonding structure), dies 242 and 256 (second semiconductor dies; second bonding structure), and bridge interconnects 104 (third bonding structure).).
Regarding claim 8, Mahajan teaches a support substrate, wherein the gap filling layer, the second semiconductor dies and the bridge die are disposed between the support substrate and the first semiconductor die (Fig. 1 points to an alternative embodiment of an IC assembly comprising dies 102 (second semiconductor dies), a bridge 120 (bridge die), a heat spreader 122 (first semiconductor die), an electrically insulative material 124 (gap filling layer) and a package substrate 104 (support substrate).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Mahajan, such that a support substrate is formed in order to provide a form of housing that would allow for increased protection and physical stability.
Regarding claim 9, Yu teaches wherein the dummy region continuously extends from a first integrated circuit region among the integrated circuit regions to a second integrated circuit region among the integrated circuit regions (Fig. 1 points to the integrated circuit dies 105 and the encapsulant 103 (dummy region).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow and Yu, such that the dummy region is a continuous extension between the first and second integrated circuit regions in order to improve physical stability by forming a single united layer that provides lateral electrical isolation between each of the integrated circuit regions.
Regarding claim 10, Chow teaches a structure comprising: a first semiconductor die comprising a first integrated circuit region, and a second integrated circuit region (Fig. 2 points to substrates 108 and 110 (first semiconductor die).); second semiconductor dies disposed over and electrically connected to the first integrated circuit region and the second integrated circuit region (Id. points to integrated circuit dies 242 and 256 (second semiconductor dies).); and a bridge die disposed over and electrically connected to the first integrated circuit region and the second integrated circuit region (Id. points to a bridge integrated circuit package system 102).
Chow fails to teach a dummy region, wherein the second integrated circuit region is connected to the first integrated circuit region through the dummy region.
Yu teaches a dummy region, wherein the second integrated circuit region is connected to the first integrated circuit region through the dummy region. (Fig. 1 points to the integrated circuit dies 105 and the encapsulant 103 (dummy region).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow and Yu, such that a dummy region is formed to connect the first and second integrated circuit regions in order to improve physical stability by forming a single united layer that provides lateral electrical isolation between each of the integrated circuit regions.
Claim(s) 7 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chow et al. in further view of Wang (WO 2022246603).
Regarding claim 7, Chow teaches wherein the second semiconductor dies are arranged side-by-side on the first semiconductor die, and the bridge die is disposed between the second semiconductor dies (Fig. 2 points to the substrates 108 and 110 (first semiconductor substrate), the circuit dies 242 and 256 (second semiconductor dies), and the bridge integrated circuit package system 102 (bridge die).), and a top surface of the gap filling layer substantially levels with back surfaces of the second semiconductor dies and a top surface of the bridge die.
Chow fails to teach a top surface of the gap filling layer substantially levels with back surfaces of the second semiconductor dies and a top surface of the bridge die.
Mahajan in combination with Wang teaches a top surface of the gap filling layer substantially levels with back surfaces of the second semiconductor dies and a top surface of the bridge die (Fig. 4 of Mahajan points to the electrically insulating material 312 (gap filling layer) being substantially level with the bridge 310 (bridge die). Fig. 5 of Wang points to a chip packaging structure comprising an interconnection bridge 12 (bridge die) that is substantially level with dies 11a and 11b (second semiconductor dies).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Wang, such that the gap filling layer, back surfaces of the second semiconductor dies, and a top surface of the bridge die together create a substantially level surface in order to reduce the critical dimensions of the overall structure and/or improve physical stability by creating a single flat surface.
Regarding claim 11, Mahajan in combination with Wang teaches a gap filling layer laterally encapsulating the bridge die and the second semiconductor dies (Figs. 3-4 and [0035] of Mahajan point to an integrated circuit (IC) package comprising an electrically insulating material 312 (gap fill layer) such as a molding compound.).Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Mahajan, such that a gap filling layer is formed to laterally encapsulate the bridge die and the second semiconductor dies in order to provide a level of electrical insulation between each of the dies, wherein a top surface of the gap filling layer substantially levels with back surfaces of the second semiconductor dies and a top surface of the bridge die (Fig. 4 of Mahajan points to the electrically insulating material 312 (gap filling layer) being substantially level with the bridge 310 (bridge die). Fig. 5 of Wang points to a chip packaging structure comprising an interconnection bridge 12 (bridge die) that is substantially level with dies 11a and 11b (second semiconductor dies).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Wang, such that the gap filling layer, back surfaces of the second semiconductor dies, and a top surface of the bridge die together create a substantially level surface in order to reduce the critical dimensions of the overall structure and/or improve physical stability by creating a single flat surface.
Regarding claim 12, Mahajan teaches an adhesive layer; and a support substrate, wherein the support substrate is adhered to the gap filling layer, the second semiconductor dies and the bridge die by the adhesive layer (Fig. 1 point to a package substrate 104 (support substrate) attached to an IC package 108 comprising dies 102 (second semiconductor dies), a bridge 120 (bridge die), and an electrically insulative material 124 (gap filling layer). [0025] further points to the package substrate 104 being an epoxy-based laminate substrate comprising a core (support substrate) and/or build-up layers (adhesive layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Mahajan, such that a support substrate and an adhesive layer are formed in order to provide a form of housing that would allow for increased protection and physical stability.
Regarding claim 13, Mahajan teaches wherein sidewalls of the support substrate substantially align with sidewalls of the gap filling layer and sidewalls of the first semiconductor die (Fig. 1 points to the package substrate 104 (support substrate), an electrically insulative material 124 (gap filling layer), and the heat spreader 122 (first semiconductor die).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Mahajan, such that the sidewalls of the support substrate substantially align with those of the gap filling layer and the first semiconductor die in order to streamline the fabrication process and/or provide uniformity to the device as a whole.
Regarding claim 14, Mahajan teaches wherein the support substrate and the first semiconductor die are substantially identical in lateral dimension (Fig. 1 points to the heat spreader 122 (first semiconductor die) and the package substrate 104 (support substrate), which is only slightly larger in terms of its lateral dimension. It is considered obvious the said substrate 104 could be trimmed/etched such that it matches the dimension(s) of the heat spreader 122 in order to reduce the critical dimensions of the device.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Mahajan, such that the support substrate laterally aligns with the first semiconductor die in order to streamline the fabrication process and/or reduce the critical dimensions of the device.
Regarding claim 15, Chow teaches wherein the second semiconductor dies and the bridge die are substantially identical in thickness (Fig. 2 points to the circuit dies 242 and 256 (second semiconductor dies) and the bridge integrated circuit die 222.).
Chow fails to teach wherein the second semiconductor dies and the bridge die are located at a same level height.
Wang teaches wherein the second semiconductor dies and the bridge die are located at a same level height (Fig. 5 points to the dies 11a and 11b (second semiconductor dies) and the interconnection bridge 12 (bridge die).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Wang, such that the second semiconductor dies and the bridge die are located at a same level height in order to reduce the critical dimensions of the overall structure and/or improve physical stability by creating a single flat surface.
Regarding claim 16, Chow teaches a structure, comprising: a first semiconductor die comprising integrated circuit regions and a bonding structure, wherein the bonding structure covers the integrated circuit regions (Fig. 2, [0045], and [0047] point to substrates 108 and 110 (first semiconductor substrate), and top surfaces 246 and 260 (bonding structure).); second semiconductor dies disposed over and electrically connected to the integrated circuit regions through the bonding structure (Id. points to integrated circuit dies 242 and 256 (second semiconductor dies).); and a bridge die disposed over the bonding structure and electrically connected to the integrated circuit regions through the bonding structure (Id. points to a bridge integrated circuit package system 102).
Chow fails to teach wherein the integrated circuit regions are laterally connected to each other, and wherein the second semiconductor dies and the bridge die are located at a same level height.
Yu teaches wherein the integrated circuit regions are laterally connected to each other (Fig. 1 points to the integrated circuit dies 105 and the encapsulant 103.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow and Yu, such that the integrated circuit regions are laterally connected to each other in order to improve physical stability by forming a single united layer.
Chow et al. fails to teach wherein the second semiconductor dies and the bridge die are located at a same level height.
Wang teaches wherein the second semiconductor dies and the bridge die are located at a same level height (Fig. 5 points to the dies 11a and 11b (second semiconductor dies) and the interconnection bridge 12 (bridge die).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Wang, such that the second semiconductor dies and the bridge die are located at a same level height in order to reduce the critical dimensions of the overall structure and/or improve physical stability by creating a single flat surface.
Regarding claim 17, Chow in combination with Mahajan teaches a gap filling layer laterally encapsulating the bridge die and the second semiconductor dies (Figs. 3-4 and [0035] of Mahajan point to an integrated circuit (IC) package comprising an electrically insulating material 312 (gap fill layer) such as a molding compound.), wherein the gap filling layer, the second semiconductor dies and the bridge die are substantially identical in thickness (Fig. 3 and [0035] of Mahajan point to removing excess electrically insulating material 312 (gap fill layer) according to operation 207, where in some embodiments all excess material is removed. Fig. 2 of Chow further points to the circuit dies 242 and 256 (second semiconductor dies) and the bridge integrated circuit die 222.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Mahajan, such that each of the dies and the gap filling layer are formed/trimmed to be substantially identical in thickness in order to reduce critical dimensions and/or apply uniformity to the device.
Regarding claim 18, Mahajan teaches a support substrate, wherein the support substrate is adhered to the gap filling layer, the second semiconductor dies and the bridge die (Fig. 1 point to a package substrate 104 (support substrate) attached to an IC package 108 comprising dies 102 (second semiconductor dies), a bridge 120 (bridge die), and an electrically insulative material 124 (gap filling layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Mahajan, such that a support substrate is formed in order to provide a form of housing that would allow for increased protection and physical stability.
Regarding claim 19, Mahajan teaches wherein sidewalls of the support substrate substantially align with sidewalls of the gap filling layer and sidewalls of the first semiconductor die (Fig. 1 points to the package substrate 104 (support substrate), an electrically insulative material 124 (gap filling layer), and the heat spreader 122 (first semiconductor die).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow et al. and Mahajan, such that the sidewalls of the support substrate substantially align with those of the gap filling layer and the first semiconductor die in order to streamline the fabrication process and/or provide uniformity to the device as a whole.
Regarding claim 20, Chow in combination with Yu teaches wherein the first semiconductor die further comprises a dummy region located between the integrated circuit regions, the dummy region extends continuously between the integrated circuit regions, the bridge die is disposed over and covers the dummy region, and the integrated circuit regions are spaced apart from each other by the dummy region (Fig. 1 of Yu points to a semiconductor device 100 comprising integrated circuit dies 105 and an encapsulant 103 (dummy region). Fig. 2 of Chow points to the bridge integrated circuit package system 102.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Chow and Yu, such that a dummy region is formed between the integrated circuit regions and underneath the bridge die in order to improve physical stability by forming a single united layer that provides lateral electrical isolation between each of the integrated circuit regions.
Response to Arguments
Applicant’s arguments, see Remarks, filed 03/31/2026, with respect to the rejection of claim 4 under 35 U.S.C. §112(d) have been fully considered and are persuasive. The rejection of said claim has been withdrawn.
Applicant’s arguments, see Remarks, filed 03/31/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chow et al. in further view of Yu (US Patent No. 9496189) and/or Wang (WO 2022246603).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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