DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group II, claims 14-20 and new claims 21-33 in the reply filed on 2/26/26 is acknowledged.
Applicant’s cancellation of non-elected claims 1-13 is acknowledged.
Allowable Subject Matter
Claims 15-17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21-33 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 21, the limitation “wherein an upper surface of each of the protection elements… is not lower than a lower surface of the topmost one of the channel layer(s)…” is indefinite in view of Applicant’s fig. 27.
In fig. 27, the channel protection element (751) is lower than a lower surface of the topmost one of the channel layer(s) (e.g. 723 top).
Claim 26 recites similar limitations so the same rejection applies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pan et al., US Publication No. 2021/0134677 A1.
Pan anticipates:
14. A method for manufacturing a semiconductor structure, comprising (see figs. 29-30):
forming a first device (e.g. transistor in region 702 in fig. 29A) that includes
two first source/drain regions (820) spaced apart from each other in a first direction (x-dir) transverse to a second direction (z-dir) from bottom to top of the first device,
two isolation elements (730 in fig. 26), each of which is disposed below a respective one of the first source/drain regions (e.g. In fig. 26, isolation 730 has a height below layer 711 and in fig. 28A the etching stops at layer716. The height of source/drain regions 820 extends up to 716 in fig. 29A. The isolation 730 is below the source/drain regions because its height is below the height of the source/drain regions.)
a first channel feature (766A, 766B) including at least one first effective channel layer and at least one dummy channel layer (762A, 762B) that are spaced apart from each other in the second direction, each of the at least one first effective channel layer (766A, 766B) extending between the two first source/drain regions (820), each of the at least one dummy channel layer (762A, 762B) extending between the two isolation elements (730) (e.g. In fig. 26, isolation 730 is disposed in the trench so it is between the dummy channel layers 762A, 762B.)
at least one semiconductor layer (764A, 764B) at least covering a lower surface of a bottommost one of the at least one dummy channel layer (762A, 762B), and
a first gate feature (850A, 850B) disposed around the at least one first effective channel layer such that two surfaces of each of the at least one first effective channel layer, which are opposite to each other in the second direction, are adjacent to the first gate feature; and
forming a second device (e.g. transistor in region 704 in fig. 29B) that includes
two second source/drain regions (830) spaced apart from each other in the first direction,
a second channel feature (776A, 776B) including a plurality of second effective channel layers that are spaced apart from each other in the second direction, each of the second effective channel layers extending between the two second source/drain regions, a total number of the second effective channel layers being equal to a total number of the at least one first effective channel layer and the at least one dummy channel layer (e.g. the total number is four), and
a second gate feature (860A, 860B) disposed around the second effective channel layers such that two surfaces of each of the second effective channel layers, which are opposite to each other in the second direction, are adjacent to the second gate structure. See Pan at para. [0001] – [0060], figs. 1-30.
18. The method according to claim 14, wherein each of the isolation elements (730) is made of an un-doped semiconductor material or a dielectric material, para. [0051].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
20 May 2026
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