Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/6/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities: “second lateral side” in line 10. For the sake of compact prosecution, claim 1 is interpreted in the instant Office action as follows: “second lateral side” is found to be a typographical error and is believed to be equivalent to “a second lateral side”. However, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 4 is objected to because of the following: “each of the first channels” in line 7. Although “a first lateral side of each of the first channels” is found to be supported by the original disclosure (see interpretation remarks below), meeting the standards of definiteness, and lacking any actual informalities; the examiner is noting a possible typographical error where this limitation is potentially intended to be “a first lateral side of each of the second channels” consistent with at least [0059] of the disclosure. For the sake of compact prosecution, claim 4 is interpreted in the instant Office action as follows: No actual change to the claim language has been applied during examination of the instant set of claims. The examiner is interpreting the limitation in the instant Office action as describing a spatial configuration including indirectly “vertically along a first lateral side of each of the first channels”. This interpretation is to be confirmed by applicant in next office action.
Claim 11 is objected to because of the following informalities: “between the between the” in line 8. For the sake of compact prosecution, claim 11 is interpreted in the instant Office action as follows: “between the between the” is found to be a typographical error and is believed to be equivalent to “between the”. However, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 12 is objected to because of the following informalities: “first stack channels” in line 2. For the sake of compact prosecution, claim 12 is interpreted in the instant Office action as follows: “first stack channels” is found to be a typographical error and is believed to be equivalent to “stacked first channels”. However, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 13 is objected to because of the following informalities: “between the between the” in line 9. For the sake of compact prosecution, claim 13 is interpreted in the instant Office action as follows: “between the between the” is found to be a typographical error and is believed to be equivalent to “between the”. However, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 14 is objected to because of the following informalities: “second dielectric wall structure” in line 1. For the sake of compact prosecution, claim 14 is interpreted in the instant Office action as follows: “second dielectric wall structure” is found to be a typographical error and is believed to be equivalent to “a second dielectric wall structure”. However, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 (and dependent claims 6-7 dependent therefrom), 6 (and dependent claim 7 dependent therefrom), 10, 15, 16, and 19 (and dependent claim 20 dependent therefrom) are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “the second gate dielectric wall structure” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 5 is interpreted in the instant Office action as follows: “the second gate dielectric wall structure” is equivalent to “the second dielectric wall structure” based on antecedence in claim 1. This interpretation is to be confirmed by applicant in the next office action.
Regarding claim 6, “the gate dielectric” in line 2 is unclear whether it is referring to the “first gate dielectric” recited in claim 1, the “second gate dielectric” recited in claim 4, both of these dielectrics, or some other dielectric. For the sake of compact prosecution, claim 6 is interpreted in the instant Office action as follows: “the gate dielectric” in line 2 is referring to both of these dielectrics and is equivalent to “each of the first and second gate dielectrics”. This interpretation is to be confirmed by applicant in next office action.
Claim 10 recites the limitation “the first gate metal” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 10 is interpreted in the instant Office action as follows: “the first gate metal” is equivalent to “the first metal” based on antecedence in line 2. This interpretation is to be confirmed by applicant in the next office action.
Claim 15 recites the limitation “the first wall structure” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 15 is interpreted in the instant Office action as follows: “the first wall structure” is equivalent to “the second dielectric wall structure” based on antecedence in claim 14 and based on the original disclosure showing substantially similar features (at least Fig. 1V: coupling structure 178 pn top of wall structure 176 and in contact with columns 171). This interpretation is to be confirmed by applicant in the next office action.
Claim 16 recites the limitation “the second wall portion” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 16 is interpreted in the instant Office action as follows: “the second wall portion” is equivalent to “the second dielectric wall structure” based on antecedence in claim 14. This interpretation is to be confirmed by applicant in the next office action.
Claim 19 recites the limitation “the dielectric wall structure” in line 3 (two instances). There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 19 is interpreted in the instant Office action as follows: “the dielectric wall structure” is referring to “a wall structure” in line 1 and each of the two instances are equivalent to “the wall structure”. This interpretation is to be confirmed by applicant in the next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu (US 20230015372 A1).
Regarding claim 1, Wu discloses an integrated circuit (Fig. 14C), comprising:
a first transistor (transistor at 204B) including:
a plurality of stacked first channels (206 of 204B);
a first gate dielectric (not shown; [0049]: “a gate dielectric layer”) surrounding (230 is surrounding each channel, thus the gate dielectric must at least partially surround directly or indirectly each channel) each of the first channels;
a first gate electrode (230B of 204B) including:
a first vertical column portion (See annotated figure) extending vertically (Z direction) along a first lateral side (Y facing side, See annotated figure for side designation) of each of the first channels; and
a plurality of first horizontal finger portions (See annotated Figure) each protruding laterally (Y direction) from the first vertical column portion between adjacent first channels (between in the Z direction);
a first dielectric wall structure (211; {0031]: “silicon oxide”) on second lateral side of the first channels opposite the first lateral side of the first channels (See annotated figure for side designation, opposite in the Y direction); and
a second dielectric wall structure (211´; [0034]: “same materials as these included in the gate cut feature 211”) extending along (vertically along) a side of the vertical column portion (along a 1st side, See annotated figure for side designation) opposite the first channels (opposite in the Y direction).
Illustrated below are marked and annotated figures of Figs. 14A-C of Wu.
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Regarding claim 2, Wu discloses the integrated circuit of claim 1 (Fig. 14C), further comprising a dielectric helmet structure (214A) above (“above” in the Z direction without overlapping in the Z direction. See annotated figure for direction designation.) a top first channel (214A is entirely above all of channels 206), wherein a top first finger portion extends between (diagonally between, See dashed diagonal reference line in annotated figure) the dielectric helmet structure and the top first channel.
Regarding claim 3, Wu discloses the integrated circuit of claim 2 (Fig. 14C), wherein the gate dielectric (a portion of the dielectric, at position A of annotated figure) is on a bottom surface of the dielectric helmet structure (indirectly on, See annotated figure for surface designation) between the top first finger portion and the dielectric helmet structure (the portion of the gate dielectric at position A of the dielectric is between finger portion at position B and helmet 214A).
Regarding claim 4, Wu discloses the integrated circuit of claim 1 (Fig. 14C), further comprising:
a second transistor (transistor of 204C) including:
a plurality of stacked second channels (206 of 204C);
a second gate dielectric (not shown; [0049]: “a gate dielectric layer”) surrounding (230 is surrounding each channel, thus the gate dielectric must at least partially surround directly or indirectly each channel) surrounding each of the second channels;
a second gate electrode (230B of 204C) including:
a second vertical column portion (See annotated figure) extending vertically (Z direction) along a first lateral side (See annotated figure for side designation) of each of the first channels; and
a plurality of second horizontal finger portions (See annotated Figure) each protruding laterally (in the Y direction) from the second vertical column portion and filling a space between adjacent second channels (between in the Z direction), wherein the second dielectric wall structure extends along a side of the second vertical column portion (along the “2nd Lateral Side”) opposite the second channels (opposite in the Y direction).
Regarding claim 5 as noted in the 112(b) rejection, Wu discloses the integrated circuit of claim 4 (Fig. 14C), further comprising a conductive gate coupling structure (See annotated figure, a portion of 230B) on top of the second dielectric wall structure (adirectly on top in the Z direction) and in contact with the first vertical column portion (integrally formed contact) and the second vertical column portion (integrally formed contact).
Regarding claim 6 as noted in the 112(b) rejection, Wu discloses the integrated circuit of claim 5 (Fig. 14C), wherein the conductive gate coupling structure is in contact with each of the first and second gate dielectrics (at least indirect contact).
Regarding claim 7, Wu discloses the integrated circuit of claim 6 (Fig. 14C), further comprising a lower metal connector (See annotated figure) extending below the second dielectric wall structure (below in the Z direction) and electrically coupling (integrally electrically coupling) the first vertical column portion to the second vertical column portion.
Regarding claim 8, Wu discloses the integrated circuit of claim 1 (Fig. 14C), wherein the first column portion and the first finger portions are a same first metal (These structures are integrally formed, thus they are the same material).
Regarding claim 9, Wu discloses the integrated circuit of claim 8 (Fig. 14C), further comprising a second metal ([0049]: “at least one work function metal layer”) in contact with the first gate dielectric between the stacked first channels, wherein each first finger portion is positioned between vertically adjacent portions of the second metal (the same shape of 230B is retained here while including the work function layer between the first fingers and the gate dielectric).
Regarding claim 10, Wu discloses the integrated circuit of claim 1 (Fig. 14C), wherein the first finger portions are a first metal ([0049]: “at least one work function metal layer”. Note: TiN is selected here) and the first vertical column portion is a second metal ([0049]: “bulk conductive layer”. Note: W is selected here) different than the first gate metal (the selected metals are different from one another).
Regarding independent claim 11, Wu discloses a method (Fig. 14C), comprising:
forming a first dielectric helmet structure (214A) above (“above” in the Z direction. See annotated figure for direction designation.) stacked first channels (206 of 204B) of a first transistor (transistor at 204B);
forming a first gate dielectric (not shown; [0049]: “a gate dielectric layer”) on the stacked first channels (at least indirectly on) and on a bottom surface of the first dielectric helmet structure (indirectly on. See annotated figure for direction designation); and
forming a first gate electrode (230B of 204B) including a first vertical column portion (See annotated figure) extending vertically (Z direction) along a first lateral edge (Y facing edge, See annotated figure for edge designation) of each of the stacked first channels and
a first finger portion (See annotated Figure) extending laterally (Y direction) from the first vertical column portion between the between (See diagonal dashed reference line A, where the finger is between helmet 214A and channel 206) the first dielectric helmet structure and a top first channel (See annotated figure for “top” designation) of the stacked first channels.
Regarding claim 12, Wu discloses the method of claim 11 (Fig. 14C), further comprising forming a first dielectric wall structure (211; {0031]: “silicon oxide”) extending along (indirectly along) a second lateral side of each of the first stack channels (See annotated figure for side designation).
Regarding claim 13, Wu discloses the method of claim 12 (Fig. 14C), further comprising:
forming a second dielectric helmet structure (272) above (above in the Z direction) stacked second channels (206 of 204C) of a second transistor (transistor of 204C);
forming a second gate dielectric (not shown; [0049]: “a gate dielectric layer”) surrounding (230 is surrounding each channel, thus the gate dielectric must at least partially surround directly or indirectly each channel) on the stacked second channels (at least indirectly on) and on a bottom surface of the second dielectric helmet structure (indirectly on); and
forming a second gate electrode (230B of 204C) including a second vertical column portion (See annotated figure) extending vertically (Z direction) along a first lateral edge (See annotated figure for edge designation) of each of the stacked second channels and
a second finger portion (See annotated Figure) extending laterally (in the Y direction) from the second vertical column portion between the between the second dielectric helmet structure (between in the Z direction) and a top second channel of the stacked second channels (See annotated figure for “top” designation).
Regarding claim 14, Wu discloses the method of claim 13 (Fig. 14C), further comprising forming second dielectric wall structure (211´; [0034]: “same materials as these included in the gate cut feature 211”) between (between in the Y direction) and in contact (at least indirect contact) with the first vertical column portion and second vertical column portion.
Regarding claim 15 as noted in the 112(b) rejection, Wu discloses the method of claim 14 (Fig. 14C), further comprising forming a conductive gate coupling structure (See annotated figure) on top of the second dielectric wall structure and in contact with (integral contact) the first and second vertical column portions.
Regarding claim 16 as noted in the 112(b) rejection, Wu discloses the method of claim 14 (Fig. 14C), wherein a lower conductive structure (See annotated figure) extends below the second dielectric wall structure (below in the Z direction) electrically coupling (integrally electrically coupling) the first vertical column portion to the second vertical column portion.
Regarding claim 17, Wu discloses the method of claim 11 (Wu: Fig. 14C), wherein forming the first gate electrode includes: forming a first gate metal on the gate dielectric; and forming the first finger portion and the first column portion from a second gate metal by selectively depositing the second gate metal on the first gate metal with a selective growth process.
Regarding independent claim 18, Wu discloses an integrated circuit (Fig. 14C), comprising:
a transistor (transistor at 204B) including:
a plurality of stacked channels (206 of 204B);
a dielectric helmet structure (214A) positioned above the stacked channels (“above” in the Z direction without overlapping in the Z direction. See annotated figure for direction designation.);
a gate dielectric (not shown; [0049]: “a gate dielectric layer”) on the stacked channels (230 is surrounding each channel, thus the gate dielectric must be at least partially directly or indirectly on each channel) and on a bottom surface of the dielectric helmet structure (at least indirectly on, See annotated figure for surface designation);
a first gate metal ([0049]: “at least one work function metal layer”) in contact with the gate dielectric on the top surface of a top channel of the stacked channels (at least indirectly on) and on the bottom surface of the dielectric helmet structure (at least indirectly on); and
a second gate metal ([0049]: “bulk conductive layer”. Note: W is selected here) in contact with the first gate metal between the top surface of the top channel (at least indirect contact) and the bottom surface of the dielectric helmet structure (at least indirect contact).
Regarding claim 19 as noted in the 112(b) rejection, Wu discloses the integrated circuit of claim 18 (Fig. 14C), further comprising a wall structure (211´; [0034]: “same materials as these included in the gate cut feature 211”) adjacent to a first lateral side of each of the stacked channels, the gate dielectric being positioned (position A, See annotated figure) on the wall structure (at least indirectly on) between the wall structure and the first gate metal (position of 230B at 214A).
Regarding claim 20, Wu discloses the integrated circuit of claim 19 (Fig. 14C), further comprising a second dielectric wall structure (211; {0031]: “silicon oxide”) on a second lateral side of each of the stacked channels (See annotated figure for side designation), wherein the second gate metal extends vertically between the second dielectric wall structure and the second lateral side of each of the stacked channels (the same shape of 230B is retained here while including the work function layer between the gate dielectric and bulk fill metal, i.e., the 2nd metal).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wu as applied to claim 11 above, and further in view of Belakrishnan (US 20180233503 A1).
Regarding claim 17, Wu discloses the method of claim 11 (Wu: Fig. 14C), wherein forming the first gate electrode includes:
forming a first gate metal ([0049]: “at least one work function metal layer”. Note: TiN is selected here) on the gate dielectric; and
forming the first finger portion and the first column portion from a second gate metal ([0049]: “bulk conductive layer”. Note: W is selected here.) by selectively depositing the second gate metal on the first gate metal with a selective growth process.
Wu fails to teach specific details regarding forming the second gate metal. Thus, Wu fails to teach the forming configuration “from a second gate metal by selectively depositing the second gate metal on the first gate metal with a selective growth process”.
Belakrishnan discloses a forming configuration ([0061]: “Metal gate material…deposited”) from a second gate metal ([0061]: “Metal gate material” is the second metal formed on a first metal [0061]: “deposited on the…surface of the barrier layer”) by selectively depositing ([0061]: “Metal gate material is selectively or non-selectively deposited on the treated or untreated surface of the barrier layer”) the second gate metal on the first gate metal with a selective growth process.
Modifying the method of Wu by including the selective growth process of Belakrishnan would arrive at the claimed forming configuration of the second gate metal. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because the second metals are materials overlapping in scope with the materials disclosed by Wu (Belakrishnan: [0061]: “metals such as tungsten (W). Non-limiting examples of other suitable conductive metals include aluminum (Al), platinum (Pt), gold (Au), titanium (Ti), or any combination thereof”; Wu: [0049]: “The bulk conductive layer may include Cu, W, Al, Co, Ru, other suitable materials, or combinations thereof”). A person of ordinary skill in the art would have been motivated to do so because Belakrishnan teaches selective deposition is a technique selected from a finite selection of known suitable forming techniques (Belakrishnan: [0061]: “selectively or non-selectively deposited”). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different forming method. Thus, the claim would have been obvious because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR). MPEP 2143 (1)(E).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817