Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 18 is objected to because of the following informalities: “second portion” in line 6. For the sake of compact prosecution, claim 18 is interpreted in the instant Office action as follows: “second portion” is found to be a typographical error and is believed to be equivalent to “a second portion”. However, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: “the dielectric wall structure” in lines 3-4. For the sake of compact prosecution, claim 19 is interpreted in the instant Office action as follows: “the dielectric wall structure” is found to be a typographical error and is believed to be equivalent to “the first dielectric wall structure” because there are no other dielectric wall structures in the claim. However, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 (and dependent claim 7 dependent therefrom) and 18 (and dependent claims 19-20 dependent therefrom) are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, “the gate dielectric” in line 2 is unclear whether it is referring to the “first gate dielectric” recited in claim 1, the “second gate dielectric” recited in claim 4, both of these dielectrics, or some other dielectric. For the sake of compact prosecution, claim 6 is interpreted in the instant Office action as follows: “the gate dielectric” in line 2 is referring to both of these dielectrics and is equivalent to “each of the first and second gate dielectrics”. This interpretation is to be confirmed by applicant in next office action.
Claim 18 recites the limitation “the top channel” in line 10. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 18 is interpreted in the instant Office action as follows: “the top channel” is referring to “a highest channel of the stacked channels” in line 6. However, no actual change to the claim language has been applied during examination of the instant set of claims. This interpretation is to be confirmed by applicant in the next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-6, 8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 20220173097 A1).
Regarding claim 1, Yang discloses an integrated circuit (Fig. 25), comprising:
a first transistor (transistor at F1) including:
a first source/drain region (Fig. 17A: one of SD1);
a second source/drain region (another of SD1);
a plurality of stacked first channels (NSS) extending in a first lateral direction between (“between” in the X direction) the first source/drain region and the second source/drain region;
a first gate dielectric (152) on (directly “on”) the first channels;
a first gate electrode (Fig. 25: 160A at F1) including:
a first vertical column portion (See annotated figure) extending vertically (Z direction) along a first lateral side (Y1` side) of each of the first channels; and
a plurality of first horizontal finger portions (See annotated figure) each protruding laterally (Y direction) from the first vertical column portion between adjacent first channels (between in the Z direction);
a first dielectric wall structure (150A) on (indirectly “on”) a second lateral side (Y1 side) of the first channels opposite the first lateral side of the first channels (opposite in the Y direction) in a second lateral direction (Y direction), wherein the gate dielectric layer is positioned on a sidewall of the first dielectric wall structure (directly “on”) between (sandwiched between) a lateral end of each finger portion (See annotated figure) and the first dielectric wall structure; and
a second dielectric wall structure (150C) extending along (vertically along) a side (Y1` side) of the vertical column portion opposite the first channels (opposite in the Y direction).
Illustrated below is a marked and annotated figure of Fig. 25 of Yang.
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Regarding claim 4, Yang discloses the integrated circuit of claim 1 (Fig. 25), further comprising:
a second transistor (transistor at F2) including:
a plurality of stacked second channels (NSS);
a second gate dielectric (152) surrounding (fully surrounding) each of the second channels;
a second gate electrode (160A at F2) including:
a second vertical column portion (See annotated figure) extending vertically (Z direction) along a first lateral side (Y1 side) of each of the second channels; and
a plurality of second horizontal finger portions (See annotated Figure) each protruding laterally (in the Y direction) from the second vertical column portion and filling a space between adjacent second channels (between in the Z direction), wherein the second dielectric wall structure extends along a side of the second vertical column portion (Y1 side) opposite the second channels (opposite in the Y direction).
Regarding claim 5, Yang discloses the integrated circuit of claim 4 (Fig. 25), further comprising a conductive gate coupling structure (ML3 at 150C) on top of the second dielectric wall structure (directly “on top” in the Z direction) and in contact with the first vertical column portion (direct contact) and the second vertical column portion (direct contact).
Regarding claim 6 as noted in the 112(b) rejection, Yang discloses the integrated circuit of claim 5 (Fig. 25), wherein the conductive gate coupling structure is in contact with each of the first and second gate dielectrics (direct contact with at least a portion of 152).
Regarding claim 8, Yang discloses the integrated circuit of claim 1 (Fig. 25), wherein the first column portion and the first finger portions are a same first metal (These structures each include ML2; [0067]: “metal film”).
Regarding claim 10, Yang discloses the integrated circuit of claim 1 (Fig. 25), wherein the first finger portions are a first metal (These structures each include ML2; [0067]: “metal film”) and the first vertical column portion is a second metal (ML3; [0067]: “metal film”) different than the first gate metal ([0067] describes mutually exclusive materials lists for these gate metals, thus “different”).
Claims 11-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu (US 20230015372 A1).
Regarding independent claim 11, Wu discloses a method (Fig. 14C), comprising:
forming a first dielectric helmet structure (214A) overlying (“overlying” in the Z direction without requiring overlapping in any specific direction. See annotated figure for direction designation.) stacked first channels (206 of 204B) of a first transistor (transistor at 204B);
forming a first gate dielectric (not shown; [0049]: “a gate dielectric layer”) on the stacked first channels (at least indirectly “on”) and on a bottom surface of the first dielectric helmet structure (indirectly “on”. See annotated figure for “bottom” direction designation) overlaid by the bottom surface of the first dielectric helmet structure (“overlaid” in at least some direction); and
forming a first gate electrode (230B of 204B) including a first vertical column portion (See annotated figure) extending vertically (Z direction) along a first lateral edge (Y facing edge, See annotated figure for edge designation) of each of the stacked first channels and
a first finger portion (See annotated Figure) extending laterally (Y direction) from the first vertical column portion between (See diagonal dashed reference line A, where the finger is between helmet 214A and channel 206) the first dielectric helmet structure and a top first channel (See annotated figure for “top” designation) of the stacked first channels.
Regarding claim 12, Wu discloses the method of claim 11 (Fig. 14C), further comprising forming a first dielectric wall structure (211; {0031]: “silicon oxide”) extending along (indirectly along) a second lateral side of each of the first stacked channels (See annotated figure for side designation).
Regarding claim 13, Wu discloses the method of claim 12 (Fig. 14C), further comprising:
forming a second dielectric helmet structure (272) above (above in the Z direction) stacked second channels (206 of 204C) of a second transistor (transistor of 204C);
forming a second gate dielectric (not shown; [0049]: “a gate dielectric layer”) surrounding (230 is surrounding each channel, thus the gate dielectric must at least partially surround directly or indirectly each channel) on the stacked second channels (at least indirectly on) and on a bottom surface of the second dielectric helmet structure (indirectly on); and
forming a second gate electrode (230B of 204C) including a second vertical column portion (See annotated figure) extending vertically (Z direction) along a first lateral edge (See annotated figure for edge designation) of each of the stacked second channels and
a second finger portion (See annotated Figure) extending laterally (in the Y direction) from the second vertical column portion between the second dielectric helmet structure (between in the Z direction) and a top second channel of the stacked second channels (See annotated figure for “top” designation).
Regarding claim 14, Wu discloses the method of claim 13 (Fig. 14C), further comprising forminga second dielectric wall structure (211´; [0034]: “same materials as these included in the gate cut feature 211”) between (between in the Y direction) and in contact (at least indirect contact) with the first vertical column portion and second vertical column portion.
Regarding claim 15, Wu discloses the method of claim 14 (Fig. 14C), further comprising forming a conductive gate coupling structure (See annotated figure) on top of the second dielectric wall structure and in contact with (integral contact) the first and second vertical column portions.
Regarding claim 16, Wu discloses the method of claim 14 (Fig. 14C), wherein a lower conductive structure (See annotated figure) extends below the second dielectric wall structure (below in the Z direction) electrically coupling (integrally electrically coupling) the first vertical column portion to the second vertical column portion.
Regarding claim 17, Wu discloses the method of claim 11 (Wu: Fig. 14C), wherein forming the first gate electrode includes: forming a first gate metal on the gate dielectric; and forming the first finger portion and the first column portion from a second gate metal by selectively depositing the second gate metal on the first gate metal with a selective growth process.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 1-2, 4-10, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20230015372 A1) in view of Yang.
Regarding claim 1, Wu discloses an integrated circuit (Fig. 14C), comprising:
a first transistor (transistor at 204B) including:
a first source/drain region (Fig. 14B: region 224; [0054]: “S/D features”, corresponding to one of Fig. 14A: region 242);
a second source/drain region (Fig. 14B: region 224; [0054]: “S/D features”, corresponding to another of Fig. 14A: region 242);
a plurality of stacked first channels (206 of 204B) extending in a first lateral direction between (“between” in the X direction, because it corresponds to region 272 sandwiched between the two regions 242, See annotated figure for direction designation; [0041]: “S/D recesses…adjacent” further supports this “between” arrangement; Figs. 9A/10A shows an intermediate process which also supports this “between” arrangement) the first source/drain region and the second source/drain region;
a first gate dielectric (not shown; [0049]: “a gate dielectric layer”) on (230 is at least partially directly or indirectly “on” each channel) the first channels;
a first gate electrode (230B of 204B) including:
a first vertical column portion (See annotated figure) extending vertically (Z direction) along a first lateral side (Y facing side, See annotated figure for side designation) of each of the first channels; and
a plurality of first horizontal finger portions (See annotated figure) each protruding laterally (Y direction) from the first vertical column portion between adjacent first channels (between in the Z direction);
a first dielectric wall structure (211; {0031]: “silicon oxide”) on (indirectly “on”) a second lateral side of the first channels opposite the first lateral side of the first channels (See annotated figure for side designation, opposite in the Y direction) in a second lateral direction (Y direction, See annotated figure for direction designation), wherein the gate dielectric layer is positioned on a sidewall of the first dielectric wall structure between a lateral end of each finger portion and the first dielectric wall structure; and
a second dielectric wall structure (211´; [0034]: “same materials as these included in the gate cut feature 211”) extending along (vertically along) a side of the vertical column portion (along a 1st side, See annotated figure for side designation) opposite the first channels (opposite in the Y direction).
Illustrated below are marked and annotated figures of Figs. 14A-C of Wu.
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Wu discloses the gate dielectric layer but fails to teach specific shapes and arrangements for this layer ([0049]: “a gate dielectric layer (not depicted separately)”). Thus, Wu fails to teach the claimed arrangement:
“[…] wherein the gate dielectric layer is positioned on a sidewall of the first dielectric wall structure between a lateral end of each finger portion and the first dielectric wall structure”.
Yang discloses a gate dielectric layer (Fig. 25: layer 152; [0120]: “gate dielectric film”):
wherein the gate dielectric layer is positioned on (directly “on”) a sidewall of the first dielectric wall structure (150A) between (“between” in the Y direction) a lateral end of each finger portion (See annotated figure for end and portion designation) and the first dielectric wall structure
Modifying the gate dielectric layer configuration of Wu by incorporating the configuration disclosed by Yang would arrive at the claimed configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because the gate dielectric layers are formed using the same method (i.e., a replacement gate technique) (Wu: [0048]: “replaces the dummy gate…forms metal gate stacks”, combined with [0049]: “metal gate stack 230 includes a gate dielectric layer…and a metal gate electrode…over the gate dielectric layer”; Yang: Figs. 17A-17C shows a replacement gate technique consistent with the method described by Wu). A person of ordinary skill in the art before the effective filing date would have been motivated to incorporate the gate dielectric layer configuration (of Yang) because it would produce a functional gate using a known technique (i.e., a replacement gate technique) in the same way (as Wu) for a comparable device (the gate dielectric layer). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed gate dielectric layer configuration because it is a configuration produced by using known techniques in the same way for a comparable device. MPEP 2143 (I)(C).
Illustrated below is a marked and annotated figure of Fig. 25 of Yang.
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Regarding claim 2, Wu in view of Yang discloses the integrated circuit of claim 1 (Wu: Fig. 14C), further comprising a dielectric helmet structure (214A) overlying (“overlying” in the Z direction without requiring overlapping in any specific direction. See annotated figure for direction designation.) a top first channel (214A is entirely above all of channels 206), wherein a top first finger portion extends between (diagonally between, See dashed diagonal reference line in annotated figure) the dielectric helmet structure and the top first channel.
Regarding claim 4, Wu in view of Yang discloses the integrated circuit of claim 1 (Wu: Fig. 14C), further comprising:
a second transistor (transistor of 204C) including:
a plurality of stacked second channels (206 of 204C);
a second gate dielectric (not shown; [0049]: “a gate dielectric layer”. Note: Yang is relied upon in the same way here for the layer configuration.) surrounding (fully surrounding, as shown by Yang: Figs. 17A-17C) each of the second channels;
a second gate electrode (230B of 204C) including:
a second vertical column portion (See annotated figure) extending vertically (Z direction) along a first lateral side (along the “2nd Lateral Side”) of each of the second channels; and
a plurality of second horizontal finger portions (See annotated Figure) each protruding laterally (in the Y direction) from the second vertical column portion and filling a space between adjacent second channels (between in the Z direction), wherein the second dielectric wall structure extends along a side of the second vertical column portion (along the “2nd Lateral Side”) opposite the second channels (opposite in the Y direction).
Regarding claim 5, Wu in view of Yang discloses the integrated circuit of claim 4 (Wu: Fig. 14C), further comprising a conductive gate coupling structure (See annotated figure, a portion of 230B) on top of the second dielectric wall structure (directly “on top” in the Z direction) and in contact with the first vertical column portion (integrally formed contact) and the second vertical column portion (integrally formed contact).
Regarding claim 6 as noted in the 112(b) rejection, Wu in view of Yang discloses the integrated circuit of claim 5 (Wu: Fig. 14C), wherein the conductive gate coupling structure is in contact with each of the first and second gate dielectrics (at least indirect contact).
Regarding claim 7, Wu in view of Yang discloses the integrated circuit of claim 6 (Wu: Fig. 14C), further comprising a lower metal connector (See annotated figure) extending below the second dielectric wall structure (below in the Z direction) and electrically coupling (integrally electrically coupling) the first vertical column portion to the second vertical column portion.
Regarding claim 8, Wu in view of Yang discloses the integrated circuit of claim 1 (Wu: Fig. 14C), wherein the first column portion and the first finger portions are a same first metal (These structures are integrally formed, thus they are the same material).
Regarding claim 9, Wu in view of Yang discloses the integrated circuit of claim 8 (Wu: Fig. 14C), further comprising a second metal ([0049]: “at least one work function metal layer”) in contact with the first gate dielectric between the stacked first channels, wherein each first finger portion is positioned between vertically adjacent portions of the second metal (the same shape of 230B is retained here while including the work function layer between the first fingers and the gate dielectric).
Regarding claim 10, Wu in view of Yang discloses the integrated circuit of claim 1 (Wu: Fig. 14C), wherein the first finger portions are a first metal ([0049]: “at least one work function metal layer”. Note: TiN is selected here) and the first vertical column portion is a second metal ([0049]: “bulk conductive layer”. Note: W is selected here) different than the first gate metal (the selected metals are different from one another).
Regarding independent claim 18 as noted in the 112(b) rejection, Wu discloses an integrated circuit (Fig. 14C), comprising:
a transistor (transistor at 204B) including:
a plurality of stacked channels (206 of 204B);
a dielectric helmet structure (214A) positioned overlying the stacked channels (“overlying” in the Z direction without requiring overlapping in any specific direction. See annotated figure for direction designation.);
a gate dielectric (not shown; [0049]: “a gate dielectric layer”) on (230 is at least partially directly or indirectly “on” each channel) the stacked channels (230 is surrounding each channel, thus the gate dielectric must be at least partially directly or indirectly on each channel) and including a first portion on a top surface of a highest channel of the stacked channels (at least indirectly on 206 without requiring overlapping in any specific direction, See annotated figure for “top” direction designation) and second portion on a bottom surface of the dielectric helmet structure (at least indirectly on without requiring overlapping in any specific direction, See annotated figure for surface designation);
a first gate metal ([0049]: “at least one work function metal layer”) between the first portion of the gate dielectric and the second portion of the gate dielectric and in contact with (at least indirect “contact” in at least some direction) the first portion of the gate dielectric at a location overlying the top surface of the top channel (at least indirectly “overlying” in at least some direction) and in contact with (at least indirect “contact” in at least some direction) the second portion of the gate dielectric overlaid by the bottom surface of the dielectric helmet structure (at least indirectly “overlaid” in at least some direction); and
a second gate metal ([0049]: “bulk conductive layer”. Note: W is selected here) in contact with the first gate metal between the top surface of the top channel (at least indirect contact) and the bottom surface of the dielectric helmet structure (at least indirect contact).
Wu discloses the gate dielectric layer but fails to teach specific shapes and arrangements for this layer ([0049]: “a gate dielectric layer (not depicted separately)”). Thus, Wu fails to teach the claimed arrangement:
“a gate dielectric on the stacked channels and including a first portion on a top surface of a highest channel of the stacked channels and second portion on a bottom surface of the dielectric helmet structure;
a first gate metal between the first portion of the gate dielectric and the second portion of the gate dielectric and in contact with the first portion of the gate dielectric at a location overlying the top surface of the top channel and in contact with the second portion of the gate dielectric overlaid by the bottom surface of the dielectric helmet structure;”
Yang discloses:
a gate dielectric (Fig. 25: layer 152; [0120]: “gate dielectric film”) on the stacked channels (NSS) and including a first portion (See annotated figure) on a top surface of a highest channel of the stacked channels (directly on) and second portion on a bottom surface of the dielectric helmet structure;
a first gate metal (ML2) between (“between” in the Y direction) the first portion of the gate dielectric and the second portion of the gate dielectric and in contact with (direct contact) the first portion of the gate dielectric at a location overlying the top surface of the top channel (overlying in the Z direction) and in contact with the second portion of the gate dielectric (direct contact) overlaid by the bottom surface of the dielectric helmet structure;
Modifying the gate dielectric configuration of Wu by incorporating the configuration disclosed by Yang would arrive at the claimed configuration:
a gate dielectric (Yang: layer 152) on the stacked channels (Wu: channels 206; Yang: channels NSS) and including a first portion (Yang: the cited portion of 152) on a top surface of a highest channel of the stacked channels and second portion (Yang: the cited portion of 152) on a bottom surface of the dielectric helmet structure (Wu: helmet 214A at least indirectly “on” because the dielectric would be formed along the sides and passing beyond the bottom surface the helmet 214A in the Z direction);
a first gate metal (Wu: the same metal and position is retained from before) between the first portion of the gate dielectric and the second portion of the gate dielectric (Wu: gate 230 corresponds to Yang: gate ML2/ML3, which is between the above cited portions of 152) and in contact with the first portion of the gate dielectric at a location overlying the top surface of the top channel (Wu: gate 230 corresponds to Yang: gate ML2/ML3, which is in direct contact with the above cited portions of 152) and in contact with the second portion of the gate dielectric overlaid by the bottom surface of the dielectric helmet structure (Wu: gate 230 corresponds to Yang: gate ML2/ML3, which is in direct contact with the above cited portions of 152. Wu: helmet 214A has at least indirect “contact” because it the dielectric would be formed along the sides and passing beyond the bottom surface the helmet 214A in the Z direction);
A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because the gate dielectrics are formed using the same method (i.e., a replacement gate technique) (Wu: [0048]: “replaces the dummy gate…forms metal gate stacks”, combined with [0049]: “metal gate stack 230 includes a gate dielectric layer…and a metal gate electrode…over the gate dielectric layer”; Yang: Figs. 17A-17C shows a replacement gate technique consistent with the method described by Wu). A person of ordinary skill in the art before the effective filing date would have been motivated to incorporate the gate dielectric configuration (of Yang) because it would produce a functional gate using a known technique (i.e., a replacement gate technique) in the same way (as Wu) for a comparable device (the gate dielectric layer). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed gate dielectric layer configuration because it is a configuration produced by using known techniques in the same way for a comparable device. MPEP 2143 (I)(C).
Regarding claim 19, Wu in view of Yang discloses the integrated circuit of claim 18 (Wu: Fig. 14C), further comprising a first dielectric wall structure (211´; [0034]: “same materials as these included in the gate cut feature 211”) adjacent to a first lateral side of each of the stacked channels, the gate dielectric being positioned (position A, See annotated figure) on the first dielectric wall structure (at least indirectly on) between the dielectric wall structure and the first gate metal (position of 230B at 214A).
Regarding claim 20, Wu in view of Yang discloses the integrated circuit of claim 19 (Wu: Fig. 14C), further comprising a second dielectric wall structure (211; {0031]: “silicon oxide”) on a second lateral side of each of the stacked channels (See annotated figure for side designation), wherein the second gate metal extends vertically between the second dielectric wall structure and the second lateral side of each of the stacked channels (the same shape of 230B is retained here while including the work function layer between the gate dielectric and bulk fill metal, i.e., the 2nd metal).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 3 is the inclusion of the limitation “wherein the gate dielectric is on a bottom surface of the dielectric helmet structure overlaid by the dielectric helmet structure and vertically between the top first finger portion and the dielectric helmet structure” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “gate dielectric layer”, “dielectric helmet layer”, “vertically between”, and “top first finger portion” in combination with all other limitations in claims 3, 2, and 1. The combination of all limitations required by claim 3 establishes a particular directional and spatial arrangement of parts beyond a reasonable interpretation of the prior art.
Response to Arguments
Applicant's arguments filed 6/18/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues that “Wu does not teach or suggest “a first dielectric wall structure on a second lateral side of the first channels opposite the first lateral side of the first channels in a second lateral direction, wherein the gate dielectric layer is positioned on a sidewall of the first dielectric wall structure between a lateral end of each finger portion and the first dielectric wall structure”, as set forth in amended claim 1”. Remarks at pg. 8.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Wu in view of Yang is relied upon in the instant Office action to reject claim 1 under 35 U.S.C. 103 as necessitated by the claim amendments. Additionally, Yang is relied upon to reject the claim under 35 U.S.C. 102.
Applicant argues:
Applicant argues with respect to amended claim 11 that “Applicant respectfully notes that the structure 214 is not “overlying the stacked first channels” as set forth in amended claim 11. Instead, the structure 214 is offset laterally with respect to the channels 206 to such an extent that there is not any portion of the structure 214 is overlying any portion of the channels 206. Likewise Wu does not disclose the “first gate dielectric ... on a bottom surface of the first dielectric helmet structure overlaid by the bottom surface of the first dielectric helmet structure”.”. Remarks at pg. 9.
Examiner’s Reply:
The examiner disagrees and notes MPEP 2111 Broadest Reasonable Interpretation. The claim as written does not require specific directions for overlying. Accordingly, the rejection is maintained and has been adjusted as necessitated by claim amendment and to promote clarity of the record.
Applicant argues:
Applicant argues with respect to amended claim 18 that “Claim 18, as amended, recites “a dielectric helmet structure positioned overlying the stacked channels”, “a gate dielectric on the stacked channels and including a first portion on a top surface of a highest channel of the stacked channels and second portion on a bottom surface of the dielectric helmet structure”, and “a first gate metal between the first portion of the gate dielectric and the second portion of the gate dielectric and in contact with the first portion of the gate dielectric at a location overlying the top surface of the top channel and in contact with the second portion of the gate dielectric overlaid by the bottom surface of the dielectric helmet structure””. Remarks at pg. 9.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Wu in view of Yang is relied upon in the instant Office action to reject claim 18 under 35 U.S.C. 103 as necessitated by the claim amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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