DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
“first pad 100” should read “first pad P1a” ([0042], line 12);
“second pad 200” should read “second pad P1b” ([0042], line 12).
Appropriate correction is required.
Claim Objections
Claims 6 and 15 are objected to because of the following informalities:
“connected” should read “connecting” (claim 6, line 3 and claim 15, line 3).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9, 10 and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0276277 A1 (hereinafter “Syu”).
Regarding claim 9, Syu discloses in Fig. 1 (viewed upside down) and related text a semiconductor package (1; [0018]), comprising:
a first die (102; [0019]) and a second die (104; [0019]) disposed laterally; and
a redistribution layer structure (200; [0023]) disposed over and electrically connected to the first die and the second die, wherein:
the redistribution layer structure comprises a plurality of vias and a plurality of lines stacked alternately and electrically connected to each other (included in a plurality of metal layers 202, 204, 206; [0023]-[0024]) and embedded by a plurality of polymer layers (201, 203, 205, 207; [0023]),
the redistribution layer structure further comprises at least one pad (202b; [0024]) overlapped with and electrically connected to the first die or the second die, and
the at least one pad and lines (202c; [0024]) among the plurality of lines that are closest to the first die and the second die are located at substantially the same level.
Syu does not disclose, in the embodiment of Fig. 1, from a top view, the at least one pad has an elliptical-like shape.
Syu teaches, in the embodiment of Fig. 4, from a top view, the at least one pad (LP; [0032]) has an elliptical-like shape.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the at least one pad such that from a top view, the at least one pad has an elliptical-like shape, as taught by Syu in the embodiment of Fig. 4, in order to widen the space between two adjacent pads, thereby enabling more traces to be arranged in the space, for example four high-speed signal traces and three reference or grounded traces (Syu: [0032]).
Regarding claim 10, Syu discloses the at least one pad comprises a first pad (202b (the one electrically connected to on-chip metal pad 122 and conductive pillar bump 126); Fig. 1; [0019] and [0024]) overlapped with and electrically connected to the first die and a second pad (202b (the one electrically connected to on-chip metal pad 142 and conductive pillar bump 146); Fig. 1; [0019] and [0024]) overlapped with and electrically connected to the second die.
Regarding claim 12, Syu discloses the semiconductor package as claimed in claim 10.
Syu does not explicitly disclose from the top view, the first pad and the second pad have different lengths.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first pad and the second pad such that from the top view, the first pad and the second pad have different lengths because a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955). MPEP 2144.04(IV)(A).
Regarding claim 13, Syu discloses the plurality of vias comprise a first via (202a (integral with the first pad); Fig. 1; [0024]), a second via (202a (integral with the second pad); Fig. 1; [0024]), a third via (204a (connected to the first pad); Fig. 1) and a fourth via (204a (connected to the second pad); Fig. 1),
the first via and the third via are stacked vias respectively located on opposite surfaces of the first pad (Fig. 1),
the second via and the fourth via are stacked vias respectively located on opposite surfaces of the second pad (Fig. 1),
from the top view, a center of the third via is offset from a center of the first via (Fig. 1; can be determined from cross-sectional view), and
from the top view, a center of the fourth via is offset from a center of the second via (Fig. 1; can be determined from cross-sectional view).
Regarding claim 14, Syu discloses the plurality of vias comprise a first via (202a (integral with the first pad); Fig. 1; [0024]), a second via (202a (integral with the second pad); Fig. 1; [0024]), a third via (204a (connected to the first pad); Fig. 1) and a fourth via (204a (connected to the second pad); Fig. 1),
the first via and the third via are staggered vias respectively located on opposite surfaces of the first pad (Fig. 1),
the second via and the fourth via are staggered vias respectively located on opposite surfaces of the second pad (Fig. 1), and
from the top view, a distance between the first via and the third via is different from a distance between the second via and the fourth via (Fig. 1).
Furthermore, it has been held that the drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). MPEP 2125(I).
Claim(s) 1-5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Syu in view of US 2015/0364404 A1 (hereinafter “Chen”).
Regarding claim 1, Syu discloses in Fig. 1 (viewed upside down) and related text a semiconductor package (1; [0018]), comprising:
a first die (102; [0019]) and a second die (104; [0019]) disposed laterally; and
a redistribution layer structure (200; [0023]) disposed over and electrically connected to the first die and the second die, wherein:
the redistribution layer structure comprises a plurality of vias and a plurality of lines stacked alternately and electrically connected to each other (included in a plurality of metal layers 202, 204, 206; [0023]-[0024]) and embedded by a plurality of polymer layers (201, 203, 205, 207; [0023]),
the redistribution layer structure further comprises a first pad (202b (the one electrically connected to on-chip metal pad 122 and conductive pillar bump 126); [0019] and [0024]) overlapped with and electrically connected to the first die and a second pad (202b (the one electrically connected to on-chip metal pad 142 and conductive pillar bump 146); [0019] and [0024]) overlapped with and electrically connected to the second die, and
the first pad, the second pad and lines (202c; [0024]) among the plurality of lines that are closest to the first die and the second die are located at substantially the same level.
Syu does not disclose from a top view, the first pad and the second pad have different shapes.
Chen teaches in Figs. 12A, 12B and related text metal pads (150; [0026]) of a redistribution layer (RDL) (116; [0026]) may have a non-elongated shape such as a circle (as shown in Fig. 12A), a square, a hexagon, an octagon, or the like, or an elongated shape (as shown in Fig. 12B) ([0046]).
Syu and Chen are analogous art because they both are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Syu with the specified features of Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first pad and the second pad such that from a top view, the first pad and the second pad have different shapes, in order to accommodate differences between the first die and the second die (e.g., I/O density, functionality, and the shapes of the corresponding terminals on the active surfaces of the dies, respectively), and to improve the reliability of the semiconductor package (Chen: [0046]).
Moreover, it has been held that change in shape, in the absence of persuasive evidence that the particular configuration is significant, is a matter of design choice involving only ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04(IV)(B).
Regarding claim 2, Syu in view of Chen disclose the semiconductor package as claimed in claim 1.
Syu does not disclose from the top view, the first pad and the second pad extend along different directions.
Chen teaches in Figs. 12A-12B from the top view, the first pad (150; [0046]) and the second pad (150; [0046]) extend along different directions (in Figs. 12A and 12B, the metal pad 150 extends in both of orthogonal directions in the horizontal plane).
Syu and Chen are analogous art because they both are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Syu in view of Chen with the specified features of Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first pad and the second pad such that from the top view, the first pad and the second pad extend along different directions, as taught by Chen, in order to configure each of the first pad and the second pad with a surface area adequate to permit an overlying via to land securely on the pad.
Regarding claim 3, Syu in view of Chen disclose the semiconductor package as claimed in claim 1.
Syu in view of Chen do not explicitly disclose from the top view, the first pad and the second pad have different lengths.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first pad and the second pad such that from the top view, the first pad and the second pad have different lengths because a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955). MPEP 2144.04(IV)(A).
Regarding claim 4, Syu in view of Chen disclose the plurality of vias comprise a first via (Syu: 202a (integral with the first pad); Fig. 1; [0024]), a second via (Syu: 202a (integral with the second pad); Fig. 1; [0024]), a third via (Syu: 204a (connected to the first pad); Fig. 1) and a fourth via (Syu: 204a (connected to the second pad); Fig. 1),
the first via and the third via are stacked vias respectively located on opposite surfaces of the first pad (Syu: Fig. 1),
the second via and the fourth via are stacked vias respectively located on opposite surfaces of the second pad (Syu: Fig. 1),
from the top view, a center of the third via is offset from a center of the first via (Syu: Fig. 1; can be determined from cross-sectional view), and
from the top view, a center of the fourth via is offset from a center of the second via (Syu: Fig. 1; can be determined from cross-sectional view).
Regarding claim 5, Syu in view of Chen disclose the plurality of vias comprise a first via (Syu: 202a (integral with the first pad); Fig. 1; [0024]), a second via (Syu: 202a (integral with the second pad); Fig. 1; [0024]), a third via (Syu: 204a (connected to the first pad); Fig. 1) and a fourth via (Syu: 204a (connected to the second pad); Fig. 1),
the first via and the third via are staggered vias respectively located on opposite surfaces of the first pad (Syu: Fig. 1),
the second via and the fourth via are staggered vias respectively located on opposite surfaces of the second pad (Syu: Fig. 1), and
from the top view, a distance between the first via and the third via is different from a distance between the second via and the fourth via (Syu: Fig. 1).
Furthermore, it has been held that the drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). MPEP 2125(I).
Regarding claim 11, Syu discloses the semiconductor package as claimed in claim 10.
Syu does not disclose from the top view, the first pad and the second pad extend along different directions.
Chen teaches in Figs. 12A-12B from the top view, the first pad (150; [0046]) and the second pad (150; [0046]) extend along different directions (in Figs. 12A and 12B, the metal pad 150 extends in both of orthogonal directions in the horizontal plane).
Syu and Chen are analogous art because they both are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Syu with the specified features of Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first pad and the second pad such that from the top view, the first pad and the second pad extend along different directions, as taught by Chen, in order to configure each of the first pad and the second pad with a surface area adequate to permit an overlying via to land securely on the pad.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Syu in view of Chen as applied to claim 1 above, and further in view of US 2022/0108957 A1 (hereinafter “May”).
Regarding claim 6, Syu in view of Chen disclose the semiconductor package as claimed in claim 1.
Syu in view of Chen do not disclose a bridge die disposed over the first die and the second die and electrically connecting the first die with the second die through the first pad and the second pad.
May teaches in Fig. 1 (viewed upside down) and related text a bridge die (104; [0015] and [0020]) disposed over the first die (108; [0020]) and the second die (110; [0020]) and electrically connecting the first die with the second die through the first pad (124 (corresponding to first die 108); [0022]) and the second pad (124 (corresponding to second die 110); [0022]).
Syu, Chen and May are analogous art because they each are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Syu in view of Chen with the specified features of May because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide a bridge die disposed over the first die and the second die and electrically connecting the first die with the second die through the first pad and the second pad, as taught by May, in order to provide electrical interconnections between the first die and the second die (May: [0015]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Syu in view of Chen as applied to claim 1 above, and further in view of US 2019/0304912 A1 (hereinafter “Ecton”).
Regarding claim 7, Syu in view of Chen disclose the semiconductor package as claimed in claim 1.
Syu in view of Chen do not disclose the first pad is electrically connected with the second pad through a line among the plurality of lines that extends across a gap between the first die and the second die and two vias among the plurality of vias that are respectively located between the line and the first pad and between the line and the second pad.
Ecton teaches in Fig. 1A and related text the first pad (conductor between 116 and 118; [0035] and [0037]) is electrically connected with the second pad (conductor between 116’ and 118; [0035] and [0037]) through a line (111; [0028]) among the plurality of lines that extends across a gap between the first die (104; [0029]) and the second die (104’; [0029]) and two vias (116, 116’; [0038]) among the plurality of vias that are respectively located between the line and the first pad and between the line and the second pad.
Syu, Chen and Ecton are analogous art because they each are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Syu in view of Chen with the specified features of Ecton because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to electrically connect the first pad with the second pad through a line among the plurality of lines that extends across a gap between the first die and the second die and two vias among the plurality of vias that are respectively located between the line and the first pad and between the line and the second pad, as taught by Ecton, in order to enable electrical communication between the first die and the second die.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Syu in view of Chen as applied to claim 1 above, and further in view of US 2021/0375708 A1 (hereinafter “Kuo”).
Regarding claim 8, Syu in view of Chen disclose the semiconductor package as claimed in claim 1.
Syu in view of Chen do not explicitly disclose a distance between die connectors of the first die and the second die is less than or equal to 18μm.
Kuo teaches a distance between die connectors is less than or equal to 18μm (claim 16).
Syu, Chen and Kuo are analogous art because they each are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Syu in view of Chen with the specified features of Kuo because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a distance between die connectors to be less than or equal to 18μm, as taught by Kuo, in order to increase the input/output (I/O) density.
Therefore, Syu, Chen and Kuo in combination teach a distance between die connectors of the first die and the second die is less than or equal to 18μm.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Syu in view of May.
Regarding claim 15, Syu discloses the semiconductor package as claimed in claim 10.
Syu does not disclose a bridge die disposed over the first die and the second die and electrically connecting the first die with the second die through the first pad and the second pad.
May teaches in Fig. 1 (viewed upside down) and related text a bridge die (104; [0015] and [0020]) disposed over the first die (108; [0020]) and the second die (110; [0020]) and electrically connecting the first die with the second die through the first pad (124 (corresponding to first die 108); [0022]) and the second pad (124 (corresponding to second die 110); [0022]).
Syu and May are analogous art because they each are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Syu with the specified features of May because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide a bridge die disposed over the first die and the second die and electrically connecting the first die with the second die through the first pad and the second pad, as taught by May, in order to provide electrical interconnections between the first die and the second die (May: [0015]).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Syu in view of Ecton.
Regarding claim 16, Syu discloses the semiconductor package as claimed in claim 10.
Syu does not disclose the first pad is electrically connected with the second pad through a line among the plurality of lines that extends across a gap between the first die and the second die and two vias among the plurality of vias that are respectively located between the line and the first pad and between the line and the second pad.
Ecton teaches in Fig. 1A and related text the first pad (conductor between 116 and 118; [0035] and [0037]) is electrically connected with the second pad (conductor between 116’ and 118; [0035] and [0037]) through a line (111; [0028]) among the plurality of lines that extends across a gap between the first die (104; [0029]) and the second die (104’; [0029]) and two vias (116, 116’; [0038]) among the plurality of vias that are respectively located between the line and the first pad and between the line and the second pad.
Syu and Ecton are analogous art because they each are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Syu with the specified features of Ecton because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to electrically connect the first pad with the second pad through a line among the plurality of lines that extends across a gap between the first die and the second die and two vias among the plurality of vias that are respectively located between the line and the first pad and between the line and the second pad, as taught by Ecton, in order to enable electrical communication between the first die and the second die.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Syu in view of US 2016/0133571 A1 (hereinafter “Lee”) and Chen.
Regarding claim 17, Syu discloses in Fig. 1 (viewed upside down) and related text a method of forming a semiconductor package (1; [0018]), comprising:
providing a first die (102; [0019]) and a second die (104; [0019]);
forming a redistribution layer structure (200; [0023]) over and electrically connected to the first die and the second die, wherein forming the redistribution layer structure comprises forming a first pad (202b (the one electrically connected to on-chip metal pad 122 and conductive pillar bump 126); [0019] and [0024]) overlapped with and electrically connected to the first die and forming a second pad (202b (the one electrically connected to on-chip metal pad 142 and conductive pillar bump 146); [0019] and [0024]) overlapped with and electrically connected to the second die; and
forming bumps (250) on the redistribution layer structure.
Syu does not disclose providing the first die and the second die on a carrier, wherein from a top view, the first pad and the second pad have different shapes, and removing the carrier.
Lee teaches providing the first die (1306) and the second die (1308) on a carrier (1300) (Fig. 13A, stage 2; [0122]), and removing the carrier (Fig. 13C, stage 12; [0132]).
Chen teaches in Figs. 12A, 12B and related text metal pads (150; [0026]) of a redistribution layer (RDL) (116; [0026]) may have a non-elongated shape such as a circle (as shown in Fig. 12A), a square, a hexagon, an octagon, or the like, or an elongated shape (as shown in Fig. 12B) ([0046]).
Syu, Lee and Chen are analogous art because they each are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Syu with the specified features of Lee and Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide the first die and the second die on a carrier, and to remove the carrier, as taught by Lee, and to form the first pad and the second pad such that from a top view, the first pad and the second pad have different shapes, in order to mechanically support the first die and the second die during the fabrication of the semiconductor package, and in order to accommodate differences between the first die and the second die (e.g., I/O density, functionality, and the shapes of the corresponding terminals on the active surfaces of the dies, respectively), and to improve the reliability of the semiconductor package (Chen: [0046]).
Moreover, it has been held that change in shape, in the absence of persuasive evidence that the particular configuration is significant, is a matter of design choice involving only ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04(IV)(B).
Allowable Subject Matter
Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, individually or in combination, does not teach or suggest “wherein regions of a first polymer layer among the plurality of polymer layers that is closest to the first die and the second die are respectively subject to a first exposure and a second exposure, wherein the first exposure and the second exposure are performed separately, and the first exposure and the second exposure are performed with a single photomask and a plurality of masking blades” as recited in claim 18, and “wherein forming the first pad or the second pad comprises forming a photoresist material layer and performing a plurality of exposures separately to the photoresist material layer with a single photomask and a plurality of masking blades” as recited in claim 19. Claim 20 depends from claim 19 and therefore would be allowable at least by virtue of its dependency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811