DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
The applicant elected invention (a), drawn to substrates with low resistivity variations. This reads on claim 13, which is withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9, 10, and 12 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Oefner, US 2017/0316929 A1.
Claim 9: Oefner discloses
a handle wafer (120);
an oxide layer (18) on the handle wafer;
“either the first side 121 of the carrier wafer 120 or the second side 112 of the device wafer 110, or both of these sides 121, 112, can be provided with an oxide layer to facilitate bonding.” [0053].
and a device layer on the oxide layer, the device layer including:
a layer of compensated silicon crystalline material (110, [0023]), the layer of compensated silicon crystalline material including a Czochralski silicon substrate.
Oefner discloses that “the doping region 125 includes p-dopants and n-dopants which can be implanted, for example, at different depth. For example, n-dopants are typically used to form an optional field stop layer within the device waver 110. For example, p-dopants are typically used to form the backside emitter region. The location of these doping regions (n-type field stop layer and p-type backside emitter region) can be controlled through the selections of the respective dopants and the implantation depth in the carrier wafer 120. As p- and n-dopants have different coefficient of diffusion, both diffuse at different rate into the device wafer 110 so that the respective n- and p-doping regions are formed at a different depth in the device wafer 110.” Diffusing both p and n dopants through the bottom surface of 110 will inevitably lead to areas of with both dopants (compensated silicon areas).
Claim 10: the Czochralski silicon substrate is free of crystalline originated particle (COP) defects. “A melting laser thermal anneal process can be employed to remove crystal defects after thinning as described above. The final thickness d2 of the device wafer 110 is typically less than 400 μm, particularly less than 200 μm or less than 150 μm.” [0086].
Claim 12: the handle wafer is a silicon wafer with a diameter of 200 mm ([0030]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Oefner in view of Zi, US 2023/0341773 A1. The density of defects is not mentioned by Oefner. However, those in the art could have performed the defect remove to the level necessary to achieve desired levels of defect removal. Furthermore, the specification contains no disclosure of either the critical nature of the claimed defect concentration or any unexpected results arising therefrom. Where patentability is said to be based upon defect concentration or upon another variable recited in a claim, the applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 1-8 and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over Oefner in view of Zi, US 2023/0341773 A1.
Claim 1: Oefner discloses
a handle wafer (120);
an oxide layer (18) on the handle wafer;
“either the first side 121 of the carrier wafer 120 or the second side 112 of the device wafer 110, or both of these sides 121, 112, can be provided with an oxide layer to facilitate bonding.” [0053].
and a device layer on the oxide layer, the device layer including:
a first epitaxial silicon layer (113) bonded to the oxide layer;
a layer of compensated silicon crystalline material (110, [0023]) on the first epitaxial silicon layer, the layer of compensated silicon crystalline material including a Czochralski silicon substrate.
Oefner discloses that “the doping region 125 includes p-dopants and n-dopants which can be implanted, for example, at different depth. For example, n-dopants are typically used to form an optional field stop layer within the device waver 110. For example, p-dopants are typically used to form the backside emitter region. The location of these doping regions (n-type field stop layer and p-type backside emitter region) can be controlled through the selections of the respective dopants and the implantation depth in the carrier wafer 120. As p- and n-dopants have different coefficient of diffusion, both diffuse at different rate into the device wafer 110 so that the respective n- and p-doping regions are formed at a different depth in the device wafer 110.” Diffusing both p and n dopants through the bottom surface of 110 will inevitably lead to areas of with both dopants (compensated silicon areas).
Oefner does not disclose a second epitaxial silicon layer on the layer of compensated silicon crystalline material. However, the wafer formed by Oefner is the beginning of what may be many different devices, and in forming a device, there are many other epitaxial layers that could be added. For example, Oefner discloses the formation of a bipolar power device ([0112]). It was known in the art to have various elements formed by epitaxy, for example, the source/drain regions (Zi [0081]). It would have been obvious to have formed a second epitaxial layer in making a bipolar power device or other devices with the wafer of Oefner, or for many other semiconductor manufacturing processes.
Claim 2: the handle wafer is a silicon wafer with a diameter of 200 mm ([0030]).
Claim 3: the oxide layer on the handle wafer is a thermally grown silicon dioxide layer with a thickness between 20 nm and 2000 nm. “The optional oxide layer 118 can be formed, for example, by a thermal treatment in an oxidizing atmosphere, for example at a temperature between 1100° C. and 1180° C.” The thickness is not disclosed; however, changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon thicknesses or upon another variable recited in a claim, the applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 4: the handle wafer (120) includes an n-doped layer (125, [0050]) below the oxide layer.
Claim 5: the first epitaxial silicon layer is a p-doped silicon layer; “The epitaxial layer or doping region 113 can form a backside emitter region or a field stop layer.” Oefner [0077]. “p-type … dopant source for out-diffusion into the device wafer 110 for forming a backside emitter region.” [0049]. Oefner does not disclose the thickness of epitaxial layer 113. However, changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon thicknesses or upon another variable recited in a claim, the applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 6: Oefner does not disclose that the layer of compensated silicon crystalline material has a thickness between about 8 µm and 12 µm. However, changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon thicknesses or upon another variable recited in a claim, the applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 7: The thickness is not disclosed; however, changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon thicknesses or upon another variable recited in a claim, the applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 8 the Czochralski silicon substrate has a diameter of 200 mm ([0030]) and is substantially free of crystalline originated particle (COP) defects. “A melting laser thermal anneal process can be employed to remove crystal defects after thinning as described above. The final thickness d2 of the device wafer 110 is typically less than 400 μm, particularly less than 200 μm or less than 150 μm.” [0086].
Claim 21: Oefner discloses
a handle wafer (120);
an oxide layer (18) on the handle wafer;
“either the first side 121 of the carrier wafer 120 or the second side 112 of the device wafer 110, or both of these sides 121, 112, can be provided with an oxide layer to facilitate bonding.” [0053].
and a device layer on the oxide layer, the device layer including:
a first epitaxial silicon layer (113) on the oxide layer;
a layer of non-epitaxial silicon crystalline material (110, [0023]).
Oefner does not disclose a second epitaxial silicon layer. However, the wafer formed by Oefner is the beginning of what may be many different devices, and in forming a device, there are many other epitaxial layers that could be added. For example, Oefner discloses the formation of a bipolar power device ([0112]). It was known in the art to have various elements formed by epitaxy, for example, the source/drain regions (Zi [0081]). It would have been obvious to have formed a second epitaxial layer in making a bipolar power device or other devices with the wafer of Oefner, or for many other semiconductor manufacturing processes.
Claim 22: Oefner discloses at [0050] that “the doping region 125 includes p-dopants and n-dopants which can be implanted, for example, at different depth. For example, n-dopants are typically used to form an optional field stop layer within the device waver 110. For example, p-dopants are typically used to form the backside emitter region.” As the backside emitter region is below the field stop region ([0116], FIG. 4), this would suggest to those in the art that it may be proper to have the p-dopants thicker than the n-dopants. Thus the upper part of 120 can be considered a p-type silicon wafer having an n-doped surface region, the oxide layer being formed on the n-doped surface region. Note that implanting at a particular depth typically leaves a lower-concentration of doping at shallower levels.
Claim 23: the non-epitaxial silicon crystal layer includes p-type dopant compensation with n-type dopant. Oefner discloses that “the doping region 125 includes p-dopants and n-dopants which can be implanted, for example, at different depth. For example, n-dopants are typically used to form an optional field stop layer within the device waver 110. For example, p-dopants are typically used to form the backside emitter region. The location of these doping regions (n-type field stop layer and p-type backside emitter region) can be controlled through the selections of the respective dopants and the implantation depth in the carrier wafer 120. As p- and n-dopants have different coefficient of diffusion, both diffuse at different rate into the device wafer 110 so that the respective n- and p-doping regions are formed at a different depth in the device wafer 110.” Diffusing both p and n dopants through the bottom surface of 110 will inevitably lead to areas of with both dopants (compensated silicon areas).
Claim 24: the first epitaxial silicon layer and the second epitaxial silicon layer are p-doped layers.
“The epitaxial layer or doping region 113 can form a backside emitter region or a field stop layer.” Oefner [0077]. “p-type … dopant source for out-diffusion into the device wafer 110 for forming a backside emitter region.” [0049].
“The source/drain epitaxial structures 122 may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants” (Zi [0082]).
Claim 25: the non-epitaxial silicon crystal layer is substantially free of crystalline originated particle (COP) defects. “A melting laser thermal anneal process can be employed to remove crystal defects after thinning as described above. The final thickness d2 of the device wafer 110 is typically less than 400 μm, particularly less than 200 μm or less than 150 μm.” [0086].
Claim 26: the density of defects is not mentioned. However, those in the art could have performed the defect remove to the level necessary to achieve desired levels of defect removal. Furthermore, the specification contains no disclosure of either the critical nature of the claimed defect concentration or any unexpected results arising therefrom. Where patentability is said to be based upon defect concentration or upon another variable recited in a claim, the applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 27: the non-epitaxial silicon crystal layer includes Czochralski silicon substrate ([0023]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Iyer, WO 9809804 A1, which discloses all the features of claim 1 except that the layer is compensated.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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