DETAILED ACTION
This correspondence is in response to the communications received June 28, 2026. Claims 14-18 and 21-35 are pending.
Response to Arguments
With regard to the arguments against the Kim reference not showing the recessed portion of the RDL accommodating the passive device, it is noted that the Belonio reference is used to disclose this feature. Also noted is that Kim’s Fig. 5C which has an RDL layer 100, but does not explicitly state that plural dielectric layers compose that layer. Examiner then uses the Tsai reference to teach this well known aspect of a common RDL element.
With regard to the arguments against the Belonio reference not disclosing a molding compound in their configuration, however the rejection was formulated where Kim discloses the molding compound on the RDL, so this argument is a “piecemeal analysis of references” and not considered to be convincing as the rejection as formulated has not been taken into account. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Further Belonio teaches a circuit board that redistributes circuit lines with dielectric layers, although it is not referred to as an RDL, it is quite analogous and relevant to the prior art of Kim as detailed in the rejections below.
With regard to the arguments that Chen (for claim 15) and the office action fails to teach "wherein the forming of the frontside RDL structure comprises: depositing a plurality of dielectric layers on the molded portion; and etching a distal dielectric layer of the plurality of dielectric layers to form the recessed portion in the distal dielectric layer.". This is not found to be convincing as Chen in Figs. 8A-10 is used to teach each and every one of these limitations as can be seen in the rejection of claim 15, missing no limitations and pointing explicitly to the drawing of Fig. 9. Applicant’s arguments assert failure to disclose these claimed features, when in fact they are explicitly shown, see below in screen cap and later in the rejection.
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With regard to the arguments against the Fischer, Jang, Zhai, Tsai, Barber and Braunisch references, it is noted that the rejection still stand and address each and every limitation as claimed. It is further noted that in these remarks, there are no specific arguments to rebut, other than statements asserting disagreement with the rejections under these references.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant has made no claim to the benefit of an earlier filing date.
Election/Restrictions
Applicant’s election without traverse of Group II method claims in the reply filed on March 1, 2026 is acknowledged.
Claim Objections
Claim objections to claim 31 and 32 have been withdrawn.
Claim Rejections - 35 USC § 112
Applicant’s amendment to claim 30, renders the previous 112 rejection moot and is hereby withdrawn.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 31 and 32 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The amendments made to the ranges are now considered to be “new matter”, and not originally supported. The ranges are now an open ended upper range for claim 31 and 32 appeared to be a range between two numbers which is now two open ended ranged seemingly overlapping each other.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 1A and 4, a method of forming a package structure, the method comprising:
forming a molded portion (115) including a lower encapsulation layer (140), a plurality of through vias (145) in the lower encapsulation layer (in 140) and a first semiconductor die (120) in the lower encapsulation layer (in 140);
forming a frontside redistribution layer structure 110) on the molded portion, the frontside RDL structure including a recessed portion (R110) in a distal dielectric layer of a plurality of dielectric layers on the molded portion (100 on lower surface of 110),
wherein the plurality of through vias (145) are configured to electrically couple the frontside RDL structure (110) to an upper package (40, see below Fig. 4); and
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attaching an integrated passive device (IPD) (500) to the frontside RDL structure (lower surface of 110) in the recessed portion (R110),
wherein the IPD (500) is electrically coupled to the first semiconductor die (R110 connected to 120).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366 or 12,519,086) in view of Belonio et al. (US 2020/0227356).
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Regarding claim 14, the prior art of Kim discloses in Fig. 5C, a method of forming a package structure (see title, “Semiconductor Package with Redistribution Substrate”), the method comprising:
forming a molded portion (combination of 420, 300, 220, hereinafter referred to as ‘MP’) including a lower encapsulation layer (“second molding layer 420”, ¶ 0023), a plurality of through vias (“connection structure 300”, ¶ 0023) in the lower encapsulation layer (300 in 420) and a first semiconductor die (“semiconductor chip 220”, ¶ 0023) in the lower encapsulation layer (220 in 420);
forming a frontside redistribution layer structure (“first redistribution substrate 100”, ¶ 0023) on the molded portion (100 is formed physical ‘on’ MP), the frontside RDL structure including a recessed portion (to be addressed in the combination rejection below) in a distal dielectric layer of a plurality of dielectric layers (“The first insulating layer 101 may be provided as a plurality of first insulating layers 101. The number of the first insulating layers 101 stacked sequentially may be variously changed.”, ¶ 0024. Note: this added portion of the previously identified paragraph 0024 is not a change in position, but merely further added to counter Applicant’s assertion that Kim does not teach plural dielectric layers. Applicant had full knowledge of this paragraph 0024 in last action, thus position not changed and finality is preserved. Further the distal aspect signifies the dielectric layer farthest from molded portion 100, so lowest layer of 100.) on the molded portion (100 on lower surface of MP),
wherein the plurality of through vias (the plural 300) are configured to electrically couple the frontside RDL structure to an upper package (“The connection structures 300 may be disposed on corresponding first redistribution pads 150, and may be connected to the corresponding first redistribution pads 150.”, ¶ 0062, also 300 shown directly connected to 150 of 100. Further, the “upper package” is interpreted to be the “upper package 20”, ¶ 0121. The 300 are shown to be electrically connected through 675 and 700 to chip 710 in 20, ¶ 0114); and
attaching an integrated passive device (IPD) (“passive device 800”, ¶ 0036) to the frontside RDL structure (lower surface of 100),
wherein the IPD is electrically coupled to the first semiconductor die (¶ 0049, “the voltage output from the passive device 800 may be transmitted to the second semiconductor chip 220”, further it can be seen in Fig. 5C, where 800 is electrically connected to 220 by myriad shown electrical conductors).
Kim does not disclose, “the frontside RDL structure including a recessed portion in a distal dielectric layer of a plurality of dielectric layers (note: plurality of layers already taught by Kim, just used as identifying aspect of the limitation)
…
attaching an integrated passive device (IPD) to the frontside RDL structure in the recessed portion” (italicized portion).
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The prior art of Belonio teaches in Figs. 1 and 3,
the frontside RDL structure (“trace substrate 40”, ¶ 0018, the 40 including three insulating layers of 42, 46, 48, ¶ 0021, 0022, where layer 46 is patterned to create the recess for the auxiliary device) including a recessed portion in a distal dielectric layer (layer 46 would be the equivalent dielectric layer formed away from the molding due to the position of where the device 20 is located) of a plurality of dielectric layers (plural equivalent dielectric layers being the three insulating layers of 42, 46, 48, ¶ 0021, 0022),
…
attaching a device (“die 20”, ¶ 0018, where the aspect of “integrated passive device (IPD)” has already been taught by Kim) to the frontside RDL structure in the recessed portion (in RP on lower surface of 40).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “the frontside RDL structure including a recessed portion in a distal dielectric layer of a plurality of dielectric layers …
attaching an integrated passive device (IPD) to the frontside RDL structure in the recessed portion” (italicized portion), as disclosed by Belonio in the system of Kim, for the purpose of further contributing to the z-axis form factor miniaturization. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
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Regarding claim 21, the prior art of Kim discloses in Fig. 5C, a method of forming a package structure (see title, “Semiconductor Package with Redistribution Substrate”), comprising:
forming a molded portion (combination of 420, 300, 220, hereinafter referred to as ‘MP’) including a lower encapsulation layer (“second molding layer 420”, ¶ 0023) encapsulating a first semiconductor die (“semiconductor chip 220”, ¶ 0023, where 420 encapsulates 220) and a plurality of through vias (“connection structure 300”, ¶ 0023) adjacent to the first semiconductor die (300 are adjacent to 220);
forming, on a front side of the molded portion (on lower surface of MP, 100 is formed), a frontside redistribution layer (RDL) structure (“first redistribution substrate 100”, ¶ 0023) comprising a plurality of dielectric layers (“The first insulating layer 101 may be provided as a plurality of first insulating layers 101. The number of the first insulating layers 101 stacked sequentially may be variously changed.”, ¶ 0024. Note: this added portion of the previously identified paragraph 0024 is not a change in position, but merely further added to counter Applicant’s assertion that Kim does not teach plural dielectric layers. Applicant had full knowledge of this paragraph 0024 in last action, thus position not changed and finality is preserved.) and a plurality of redistribution metal features (“under bump patterns 120, first redistribution patterns 130, first seed patterns 135, first seed pads 155, and first redistribution pads 150”, ¶ 0024);
mounting an integrated passive device (IPD) (“passive device 800”, ¶ 0036) within the portion on the exposed surface such that the IPD is electrically connected to at least one redistribution metal feature of the frontside RDL structure (800 electrically connected to 100 by 580, ¶ 0039); and
forming a plurality of solder balls (“solder balls 500”, ¶ 0114) on a board-side surface of the frontside RDL structure (lower surface of 100) adjacent to the mounted an integrated passive device (IPD) (500 adjacent to location on surface of 100 where 800 is located).
Kim does not disclose, “creating a recessed portion in a distal dielectric layer of the plurality of dielectric layers (note: plurality of layers already taught by Kim, just used as identifying aspect of the limitation) of the frontside RDL structure to expose an underlying surface”, and subsequently as a result, does not disclose, “mounting an integrated passive device (IPD) within the recessed portion on the exposed underlying surface … forming a plurality of solder balls on a board-side surface of the frontside RDL structure adjacent to the recessed portion”.
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The prior art of Belonio teaches in Figs. 1 and 3, creating a recessed portion (recess in layer 46 and the lower surface of, “trace substrate 40”, ¶ 0018, where “die 20”, ¶ 0018, is electrical connected, hereinafter referred to as ‘RP’) in a distal dielectric layer of the plurality of dielectric layers of the frontside RDL structure (“trace substrate 40”, ¶ 0018, the 40 including three insulating layers of 42, 46, 48, ¶ 0021, 0022, where the interpreted “distal dielectric layer” is layer 46) to expose an underlying surface (underneath the lowest film of 40, layer 46, a middle most film 42, is exposed which supports the 20), and subsequently as a result, would then combined with Kim, satisfy that, “mounting an integrated passive device (IPD) (20) within the recessed portion (RP) on the exposed underlying surface (exposed lower surface of middle film 42 of 40 at RP) … forming a plurality of solder balls (“solder balls 80”, ¶ 0030) on a board-side surface of the frontside RDL structure adjacent to the recessed portion (80 are adjacent to RP on lower surface of 40).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “creating a recessed portion in a distal dielectric layer of the frontside RDL structure to expose an underlying surface … mounting an integrated passive device (IPD) within the recessed portion on the exposed underlying surface … forming a plurality of solder balls on a board-side surface of the frontside RDL structure adjacent to the recessed portion”, as disclosed by Belonio in the system of Kim, for the purpose of further contributing to the z-axis form factor miniaturization. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 15, 16, 22, 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366) in view of Belonio et al. (US 2020/0227356) in view of Chen et al. (US 2017/0194226).
Regarding claim 15, the prior art of Kim et al. discloses the method of claim 14, however Belonio does not disclose,
“wherein the forming of the frontside RDL structure comprises:
depositing a plurality of dielectric layers on the molded portion; and
etching a distal dielectric layer of the plurality of dielectric layers to form the recessed portion in the distal dielectric layer.”
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Chen discloses in Fig. 8A-10, wherein the forming of the frontside RDL structure comprises:
depositing a plurality of dielectric layers on the molded portion (passivation layers 818, ¶ 0082, 825, ¶ 0087, 801, ¶ 0058, which are formed on the equivalent “molding layer” 823, ¶ 0077); and
etching a distal dielectric layer of the plurality of dielectric layers to form the recessed portion in the distal dielectric layer (829 is an “opening” in passivation layer 801. “The second openings 827 may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of second redistribution layer 821 may be used.”, ¶ 0092, then, “at the same time that the second openings 827 to expose the portions of the second redistribution layer 821 are formed, a surface device opening 829 is also formed through the second passivation layer 801.”, ¶ 0093).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the forming of the frontside RDL structure comprises:
depositing a plurality of dielectric layers on the molded portion; and
etching a distal dielectric layer of the plurality of dielectric layers to form the recessed portion in the distal dielectric layer.”, as disclosed by Chen in the system of Kim, for the purpose of disclosing the material removal step to form the recess where the auxiliary component can fit, and further aid in the aim of minimizing device size. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 16, the prior art of Kim et al. discloses the method of claim 14, however Kim fails to disclose, “further comprising:
forming an IPD underfill layer in the recessed portion between the IPD and the frontside RDL structure; and
forming a barrier ring on a bottom surface of the recessed portion, wherein the barrier ring is configured to contain a spread of the IPD underfill layer.”
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Chen discloses in Fig. 8A-10, further comprising:
forming an IPD underfill layer (“underfill material 205”, ¶ 0093) in the recessed portion (“device opening 829”, ¶ 0093) between the IPD (“first surface device 203”, ¶ 0082, which is equivalent to Kim’s IPD, which is already disclosed in the rejection of claim 14.) and the frontside RDL structure (surface of structure of dielectrics 818, 825, 801 and conductors therein).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “further comprising:
forming an IPD underfill layer in the recessed portion between the IPD and the frontside RDL structure”, as disclosed by Chen Figs. 7A-7B in the system of Kim et al. in view of Chen Figs. 8A-10, for the purpose of protecting the delicate solder connections from oxidation and mechanical shocks during manufacturing and subsequent handling. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Chen does not show in Figs. 8A-10, “forming a barrier ring on a bottom surface of the recessed portion, wherein the barrier ring is configured to contain a spread of the IPD underfill layer.”
In Fig. 10 Chen shows the spacers in the recess, but does not label them. Chen shows in Fig. 7A-7B shows the use of spacers (111 or 301, ¶ 0055) in recess (829), and therefore shows, forming a barrier ring (¶ 0055, the “spacers” 111 or 301 ring configuration shown in Fig. 7B) on a bottom surface of the recessed portion (already shown in Fig. 10), wherein the barrier ring is configured to contain a spread of the IPD underfill layer (the spread of 205 ends at spacers).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “further comprising:
forming an IPD underfill layer in the recessed portion between the IPD and the frontside RDL structure; and
forming a barrier ring on a bottom surface of the recessed portion, wherein the barrier ring is configured to contain a spread of the IPD underfill layer.”, as disclosed by Chen in the system of Kim, for the purpose of preventing the spread of underfill which could impede other neighboring electrode connections. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 22, the prior art of Kim et al. discloses the method of claim 21, and Belonio does disclose a portion of the limitations in Figs. 1 and 3,
wherein creating the recessed portion (RP, see rejection of claim 21) comprises selective removal of the distal dielectric layer (lowest layer 46 of 40, is patterned to have RP) to a depth substantially equal to a thickness of the distal dielectric layer (RP is only the thickness of 46), thereby exposing at least one of an intermediate dielectric layer (42) or a redistribution feature (and electrical connections on 42) as the underlying surface (the underlying surface of RP is exposed part of 42).
Belonio does not explicitly state how the noted material is removed, so Belonio does not disclose, “wherein creating the recessed portion comprises selectively etching the distal dielectric layer”.
Chen discloses in Fig. 8A, 8B and 9, wherein creating the recessed portion comprises selectively etching the distal dielectric layer (829 is an “opening” in passivation layer 801. “The second openings 827 may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of second redistribution layer 821 may be used.”, ¶ 0092, then, “at the same time that the second openings 827 to expose the portions of the second redistribution layer 821 are formed, a surface device opening 829 is also formed through the second passivation layer 801.”, ¶ 0093).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein creating the recessed portion comprises selectively etching the distal dielectric layer”, as disclosed by Chen in the system of Kim/Belonio, for the purpose of disclosing the material removal step to form the recess where the auxiliary component can fit, and further aid in the aim of minimizing device size. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 24, the prior art of Kim et al. discloses the method of claim 21, however Kim et al. fail to disclose, “further comprising forming an IPD underfill material in the recessed portion after mounting the IPD, wherein the recessed portion configuration contains a lateral spreading distance of the IPD underfill material along the board-side surface.”
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Chen discloses in Figs. 8A-10, “further comprising forming an IPD (equivalent IPD being element 203) underfill material (“underfill material 205”, ¶ 0058) in the recessed portion (“opening 829”, ¶ 0098) after mounting the IPD (203 is mounted first in step of Fig. 9, then 205 is deposited in Fig. 10), wherein the recessed portion configuration contains a lateral spreading distance of the IPD underfill material along the board-side surface (829 contains lateral spread of 205, Fig. 10).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “further comprising forming an IPD underfill material in the recessed portion after mounting the IPD, wherein the recessed portion configuration contains a lateral spreading distance of the IPD underfill material along the board-side surface.”, as disclosed by Chen in the system of Kim/Belonio, for the purpose of protecting the delicate solder ball connections and also preventing the spillage of underfill to areas where the underfill is not desired. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 25, the prior art of Kim et al. discloses the method of claim 24, and Kim does not disclose, “further comprising forming a barrier ring on a bottom surface of the recessed portion prior to mounting the IPD, the barrier ring configured to contain spreading of the IPD underfill material along the bottom surface.”
Chen shows in Figs. 8A-10 shows what appears to be a “spacer” inside of the recess (829), however it is not labelled or elaborated upon in the description. Chen then shows in Figs. 7A-7B, wherein the underfill is controlled by spacers (111, 301, ¶ 0055), the spacers also form a ring shape as can be seen in Fig. 7B. This spacer and ring teaching are then combined into the structure of Figs. 8A-10 within the recess. This combined teaching then results in the limitation that satisfies, “further comprising forming a barrier ring on a bottom surface of the recessed portion prior to mounting the IPD, the barrier ring configured to contain spreading of the IPD underfill material along the bottom surface.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “further comprising forming a barrier ring on a bottom surface of the recessed portion prior to mounting the IPD, the barrier ring configured to contain spreading of the IPD underfill material along the bottom surface.”, as disclosed by Chen in the system of Kim, for the purpose of preventing the spread of underfill which could impede other neighboring electrode connections. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 18 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366) in view of Belonio et al. (US 2020/0227356) in view of Fischer (US 2010/0224960).
Regarding claim 18, the prior art of Kim et al. discloses the method of claim 14, however Kim fails to disclose, “further comprising:
forming a plurality of solder balls on a board-side surface of the frontside RDL structure, wherein a distance between the board-side surface of the frontside RDL structure and an end of the plurality of solder balls is 120 µm or less.”
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Fischer discloses in Fig. 2, that the distance from the equivalent board surface (top surface of 400) has a distance from the tip of the solder ball which has a thickness (398, 399, ¶ 0038, “first and second solder bumps 398, 399 have a diameter of about 50 to 100 micrometers.”) which includes a pad thickness (393, ¶ 0037, “the first and second metal layer 393, 394 each has a thickness of about 5 to 10 micrometers.”), which therefore satisfies the limitation of,
“further comprising:
forming a plurality of solder balls on a board-side surface of the frontside RDL structure, wherein a distance between the board-side surface of the frontside RDL structure and an end of the plurality of solder balls is 120 µm or less.” In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “further comprising:
forming a plurality of solder balls on a board-side surface of the frontside RDL structure, wherein a distance between the board-side surface of the frontside RDL structure and an end of the plurality of solder balls is 120 µm or less.”, as disclosed by Fischer in the system of Kim, for the purpose of increasingly miniaturizing the dimensions of a package which would allow for more device density per unit area in a given electronics device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 29, the prior art of Kim et al. discloses the method of claim 21, however Kim fails to disclose, “wherein a standoff height of the plurality of solder balls, measured from the board-side surface of the frontside RDL structure to an outermost end of the solder balls, is 120 pm or less.”
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Fischer discloses in Fig. 2, that the distance from the equivalent board surface (top surface of 400) has a distance from the tip of the solder ball which has a thickness (398, 399, ¶ 0038, “first and second solder bumps 398, 399 have a diameter of about 50 to 100 micrometers.”) which includes a pad thickness (393, ¶ 0037, “the first and second metal layer 393, 394 each has a thickness of about 5 to 10 micrometers.”), which therefore satisfies the limitation of,
“wherein a standoff height of the plurality of solder balls, measured from the board-side surface of the frontside RDL structure to an outermost end of the solder balls, is 120 pm or less.” In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein a standoff height of the plurality of solder balls, measured from the board-side surface of the frontside RDL structure to an outermost end of the solder balls, is 120 pm or less”, as disclosed by Fischer in the system of Kim, for the purpose of increasingly miniaturizing the dimensions of a package which would allow for more device density per unit area in a given electronics device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366 or 12,519,086) in view of Belonio et al. (US 2020/0227356) in view of Jang et al. (US 2019/0006290).
Regarding claim 23, the prior art of Kim et al. discloses the method of claim 21, however Kim fails to disclose, “wherein mounting the IPD results in a distance from the board-side surface of the frontside RDL structure to a board-side surface of the IPD being 90 pm or less.”
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Jang discloses in Fig. 3A-3C, wherein mounting the IPD results in a distance from the board-side surface of the frontside RDL structure to a board-side surface of the IPD being 90 pm or less (This limitation is understood to signify the vertical dimension of the redistribution layer. “redistribution layer 11 having a thickness of several micrometers to tens of micrometers”). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein mounting the IPD results in a distance from the board-side surface of the frontside RDL structure to a board-side surface of the IPD being 90 pm or less.”, as disclosed by Jang in the system of Kim, for the purpose of increasingly miniaturizing the vertical dimensions of a package which would allow for more device density per unit area in a given electronics device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366) in view of Belonio et al. (US 2020/0227356) in view of Zhai et al. (US 2017/0018497).
Regarding claim 27, the prior art of Kim et al. discloses the method of claim 21, however Kim fails to disclose, “wherein the IPD comprises a zero-inductance integrated passive device (ZLIPD).”
Zhai discloses in ¶ 0027, wherein a packaging structure includes an inductor, with the details of, “IPD 140 may exhibit zero inductance, and may be referred to as a zero inductance integrated passive device (ZLIPD)”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the IPD comprises a zero-inductance integrated passive device (ZLIPD).”, as disclosed by Zhai in the system of Kim, for the purpose of improving the signal handling capability of the overall package electrical system. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366) in view of Belonio et al. (US 2020/0227356) in view of Tsai et al. (US 2021/0313299) in view of Chen et al. (US 2017/0194226).
Regarding claim 28, the prior art of Kim et al. discloses the method of claim 21, however Kim does not show, “further comprising, after mounting the IPD, mounting the package structure to a package substrate via the plurality of solder balls, and forming a package underfill layer between the package substrate and the board-side surface of the frontside RDL structure, wherein the package underfill layer contacts the IPD underfill material within the recessed portion.”
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Tsai discloses in Fig. 3, further comprising, after mounting the IPD (feature already disclosed by combination rejection of claim 21), mounting the package structure (package structure including 108, 110, 122, 120 to 102) to a package substrate (102) via the plurality of solder balls (104 are the equivalent electrical connections to solder balls which are already shown by Kim, the material of solder that is.), and forming a package underfill layer (“underfill material 106” , ¶ 0018) between the package substrate (102) and the board-side surface of the frontside RDL structure (lower surface of 108).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “further comprising, after mounting the IPD, mounting the package structure to a package substrate via the plurality of solder balls, and forming a package underfill layer between the package substrate and the board-side surface of the frontside RDL structure”, as disclosed by Tsai in the system of Kim et al., for the purpose of mounting the package to a global circuit board for final mounting within a device platform. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
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So Belonio shows the recessed device arrangement, but does not show that the recessed device has an underfill. Chen discloses in Fig. 10, wherein the device 203 in recess 829 has an underfill 205. By now including the underfill of Chen into the arrangement of Kim in view of Belonio, and now with the package underfill layer of Tsai, the limitation of, “wherein the package underfill layer contacts the IPD underfill material within the recessed portion”, would then be satisfied.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the package underfill layer contacts the IPD underfill material within the recessed portion.”, as disclosed by Chen in the system of Kim et al., for the purpose of protecting the delicate solder balls providing electrical signals to the package, to prevent environmental contamination or protection to mechanical shocks. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366) in view of Barber et al. (US 6,590,292) in view of Belonio et al. (US 2020/0227356) in view of Tsai et al. (US 2021/0313299).
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Regarding claim 30, the prior art of Kim discloses in Fig. 5C, a method of forming a package (see title, “Semiconductor Package with Redistribution Substrate”), comprising:
providing a molded portion (combination of 420, 300, 220, hereinafter referred to as ‘MP’) having a first semiconductor die (“semiconductor chip 220”, ¶ 0023) and through vias (“connection structure 300”, ¶ 0023) embedded in a lower encapsulation layer (300 embedded in 420, “second molding layer 420”, ¶ 0023);
forming a frontside redistribution layer (RDL) structure (“first redistribution substrate 100”, ¶ 0023) on the molded portion (100 on lower surface of MP), the frontside RDL structure having a board-side surface (lower surface of 100) and a plurality of dielectric layers (“The first insulating layer 101 may be provided as a plurality of first insulating layers 101. The number of the first insulating layers 101 stacked sequentially may be variously changed.”, ¶ 0024. Note: this added portion of the previously identified paragraph 0024 is not a change in position, but merely further added to counter Applicant’s assertion that Kim does not teach plural dielectric layers. Applicant had full knowledge of this paragraph 0024 in last action, thus position not changed and finality is preserved.) of the frontside RDL structure (100);
attaching an integrated passive device (IPD) (“passive device 800”, ¶ 0036) in the at a portion such that a board-side surface of the IPD is positioned adjacent to the board-side surface of the frontside RDL structure (800 adjacent to other surfaces of lower surface of 100);
forming solder balls (“solder balls 500”, ¶ 0114) on the board-side surface of the frontside RDL structure (lower surface of 100).
First, Kim does not disclose (from the preamble), “with enhanced thermal performance”. Looking to support for this concept in Applicant’s disclosure, it appears that the only aspect of the package that could align with this limitation, is disclosed to be the “thermally conductive underfill layer 50” (¶ 0111), which aids in the connection of the un-claimed upper portion (40) to lower portion (100) by way of solder balls (416). Kim shows an upper package (20) electrically connected by connection bumps (675, ¶ 0122) to lower package (10E), but does not show the use of a thermally conductive underfill.
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Barber shows in Fig. 1, the use of a thermally conducive underfill material (“fill material 120 may be, for example, an epoxy compound including suspended particles (i.e., filler particles) of a thermally conductive and electrically insulating material (e.g., silica or alumina).”, col. 5, lines 24-28) used between solder balls 110, chip 130 and base 100.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation feature of, “with enhanced thermal performance”, as disclosed by Barber in the system of Kim, for the purpose of improving the operating conditions for the devices, so that the excess heat can be removed and temperatures can maintain a more optimal range for longer service lifetimes. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Kim fails to disclose, “forming a recessed portion recessed into the board-side surface in a distal dielectric layer of the plurality of dielectric layers (note: plurality of layers already taught by Kim, just used as identifying aspect of the limitation) of the frontside RDL structure;
…
attaching an integrated passive device (IPD) in the recessed portion
…
forming solder balls on the board-side surface of the frontside RDL structure with a reduced standoff height enabled by the recessed attachment of the IPD”.
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The prior art of Belonio teaches in Figs. 1 and 3, forming a recessed portion (recess in layer 46 and the lower surface of, “trace substrate 40”, ¶ 0018, where “die 20”, ¶ 0018, is electrical connected, hereinafter referred to as ‘RP’) recessed into the board-side surface in a distal dielectric layer of the plurality of dielectric layers of the frontside RDL structure (“trace substrate 40”, ¶ 0018, the 40 including three insulating layers of 42, 46, 48, ¶ 0021, 0022, where the RP is formed in a discontinuity in 46 on lower side of 40. The distal aspect is met, by orienting the substrate of Belonio in the same manner shown by KIM with the integrated passive device on the lower surface of the redistribution layer.);
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attaching an integrated passive device (IPD) in the recessed portion (Kim already teaches the IPD aspect above. The equivalent element of Belonio is element 20, ¶ 0018)
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forming solder balls (“solder balls 80”, ¶ 0030) on the board-side surface of the frontside RDL structure (in Fig. 1 lower side of 40) with a reduced standoff height enabled by the recessed attachment of the IPD (the recessed element 20 is less vertically prominent than if it were not in a recess, allowing for more clearance for the solder ball compression that may occur when reflowing. The term “enabled” is understood to mean, “to supply with the means, to make feasible or possible”, which Belonio appears to satisfy).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “forming a recessed portion recessed into the board-side surface in a distal dielectric layer of the plurality of dielectric layers of the frontside RDL structure;
…
attaching an integrated passive device (IPD) in the recessed portion
…
forming solder balls on the board-side surface of the frontside RDL structure with a reduced standoff height enabled by the recessed attachment of the IPD”, as disclosed by Belonio in the system of Kim, for the purpose of further contributing to the z-axis form factor miniaturization. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Third, Kim does not disclose, “mounting the frontside RDL structure on a package substrate via the solder balls.”
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Tsai discloses in Fig. 3, further comprising,
the frontside RDL structure having a plurality of dielectric layers (“redistribution layer 108 may include one or more conductive layers and passivation layers”, ¶ 0020. This teaching included to exhibit the well known aspect of this limitation. Where Kim already teaches this.),
after mounting the IPD (feature already disclosed by combination rejection of claim 21), mounting the package structure (package structure including 108, 110, 122, 120 to 102) to a package substrate (102) via the plurality of solder balls (104 are the equivalent electrical connections to solder balls which are already shown by Kim, the material of solder that is.), and forming a package underfill layer (“underfill material 106” , ¶ 0018) between the package substrate (102) and the board-side surface of the frontside RDL structure (lower surface of 108).
mounting the frontside RDL structure (equivalent structure being “redistribution layer 108”, ¶ 0017, the “front side” being the lower surface of 108) on a package substrate (“substrates 102”, ¶ 0017) via the solder balls (“conductive structures 104 may be microbumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls”, ¶ 0017).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “the frontside RDL structure having a plurality of dielectric layers … mounting the frontside RDL structure on a package substrate via the solder balls.”, as disclosed by Tsai in the system of Kim et al., for the purpose of mounting the package to a global circuit board for final mounting within a device platform. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Fourth, Tsai does not explicitly specify that 104 are made of “solder” per se. It is understood that, “conductive structures 104 may be microbumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls”, ¶ 0017 means solder balls, but Kim shows in Fig. 5, that 500 are “solder balls 500”, ¶ 0023.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “mounting the frontside RDL structure on a package substrate via the solder balls.”, as disclosed by Kim in the teaching of Tsai, for the purpose of utilizing a reflowable metallic connection material which has been time tested and proven as effective for making electrical connections between electronic components. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366) in view of Barber et al. (US 6,590,292) in view of Belonio et al. (US 2020/0227356) in view of Tsai et al. (US 2021/0313299) in view of Fischer (US 2010/0224960).
Regarding claim 31, the prior art of Kim et al. discloses the method of claim 30, however Kim fails to disclose, “wherein a standoff height of the solder balls, measured from the board-side surface of the frontside RDL structure to an outermost end of the solder balls, is at least 10 µm [, and] less than 126 µm.”
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Fischer discloses in Fig. 2, that the distance from the equivalent board surface (top surface of 400) has a distance from the tip of the solder ball which has a thickness (398, 399, ¶ 0038, “first and second solder bumps 398, 399 have a diameter of about 50 to 100 micrometers.”) which includes a pad thickness (393, ¶ 0037, “the first and second metal layer 393, 394 each has a thickness of about 5 to 10 micrometers.”), which therefore satisfies the limitation of,
“wherein a standoff height of the solder balls, measured from the board-side surface of the frontside RDL structure to an outermost end of the solder balls, is at least 10 µm [, and] less than 126 µm.”
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein a standoff height of the solder balls, measured from the board-side surface of the frontside RDL structure to an outermost end of the solder balls, is at least 10 µm [, and] less than 126 µm.”, as disclosed by Fischer in the system of Kim, for the purpose of increasingly miniaturizing the dimensions of a package which would allow for more device density per unit area in a given electronics device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366) in view of Barber et al. (US 6,590,292) in view of Belonio et al. (US 2020/0227356) in view of Tsai et al. (US 2021/0313299) in view of Braunisch et al. (US 2009/0001528).
Regarding claim 32, the prior art of Kim et al. discloses the method of claim 30, however Kim fails to disclose, “wherein a thickness of the first semiconductor die is at least 10 µm greater than 220 µm”.
Braunisch discloses in ¶ 0016, “semiconductor die having a thickness of between approximately 50 micrometers and 400 micrometers.” In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein a thickness of the first semiconductor die is at least 10 µm greater than 220 µm”, as disclosed by Braunisch in the system of Kim, for the purpose of increasingly miniaturizing the dimensions of a package which would allow for more device density per unit area in a given electronics device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366) in view of Barber et al. (US 6,590,292) in view of Belonio et al. (US 2020/0227356) in view of Tsai et al. (US 2021/0313299) in view of Chen et al. (US 2017/0194226).
Regarding claim 33, the prior art of Kim et al. discloses the method of claim 30, however Kim fails to disclose, “wherein dispensing the IPD underfill in the recessed portion after attaching the IPD results in an underfill keep-out zone (KOZ) on the board-side surface of the frontside RDL structure having a lateral extent of 500 µm or less from an edge of the recessed portion.”
Chen discloses in ¶ 0099, “the KOZ may be reduced to a twelfth distance D.sub.12 of between about 50 μm and about 1000 μm, such as about 300 μm, on a first side of the first surface device 203 and a thirteenth distance D.sub.13 of between about 50 μm and about 1000 μm, such as about 300 μm, on a second side of the first surface device 203.”, which would satisfy the limitation of claim 33.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein dispensing the IPD underfill in the recessed portion after attaching the IPD results in an underfill keep-out zone (KOZ) on the board-side surface of the frontside RDL structure having a lateral extent of 500 µm or less from an edge of the recessed portion.”, as disclosed by Chen in the system of Kim, for the purpose of increasingly miniaturizing the dimensions of a package which would allow for more device density per unit area in a given electronics device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366) in view of Barber et al. (US 6,590,292) in view of Belonio et al. (US 2020/0227356) in view of Tsai et al. (US 2021/0313299) in view of Zhai et al. (US 2017/0018497).
Regarding claim 34, the prior art of Kim et al. discloses the method of claim 30, however Kim fails to disclose, “wherein the IPD comprises a zero-inductance integrated passive device (ZLIPD).”
Zhai discloses in ¶ 0027, wherein a packaging structure includes an inductor, with the details of, “IPD 140 may exhibit zero inductance, and may be referred to as a zero inductance integrated passive device (ZLIPD)”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the IPD comprises a zero-inductance integrated passive device (ZLIPD).”, as disclosed by Zhai in the system of Kim, for the purpose of improving the signal handling capability of the overall package electrical system. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0065366) in view of Barber et al. (US 6,590,292) in view of Belonio et al. (US 2020/0227356) in view of Tsai et al. (US 2021/0313299) in view of Chen et al. (US 2017/0194226).
Regarding claim 35, the prior art of Kim et al. discloses the method of claim 30, however Kim fails to disclose, “wherein attaching the IPD comprises forming solder bumps between the IPD and bonding pads exposed within the recessed portion, and wherein a width of the recessed portion is at least 1.5 times a width of the IPD.”
Chen shows in Fig. 8A-11, where width of opening 829 is W8 which is “about 0.1 mm and about 1 mm, such as about 200 μm”, ¶ 0094. Then Chen states in ¶ 0031, that the “device 203” has width of between 0.5mm and 5mm. In the claimed range, the given values satisfy the ratio claimed. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein attaching the IPD comprises forming solder bumps between the IPD and bonding pads exposed within the recessed portion, and wherein a width of the recessed portion is at least 1.5 times a width of the IPD”, as disclosed by Chen in the system of Kim, for the purpose of increasingly miniaturizing the dimensions of a package which would increase device density per unit area, allowing for further functionality of the overall device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claims 17 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For claim 17, the prior art of Kim et al. (US 2023/0065366) discloses in Fig. 5C, a method of forming a package structure, but lacks the specific arrangement of the integrated passive device underfill layer and UBM dam structure as claimed.
“17. (Original) The method of claim 14, further comprising:
forming an IPD underfill layer that fills the recessed portion between the IPD and the frontside RDL structure; and
forming an underbump metallization (UBM) dam structure on a board-side surface of the frontside RDL structure, wherein the UBM dam structure is configured to impede a contain of the IPD underfill layer.”
For claim 26, the prior art of Kim et al. (US 2023/0065366) discloses in Fig. 5C, a method of forming a package structure, but lacks the specific arrangement of the integrated passive device underfill layer and UBM dam structure as claimed.
“26. The method of claim 24, further comprising forming an underbump metallization (UBM) dam structure on the board-side surface of the frontside RDL structure laterally surrounding at least a portion of the recessed portion, the UBM dam structure configured to impede spreading of the IPD underfill material beyond the recessed portion.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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