Prosecution Insights
Last updated: July 17, 2026
Application No. 18/501,137

THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§112
Filed
Nov 03, 2023
Priority
Jun 18, 2020 — provisional 63/040,791 +2 more
Examiner
LI, MEIYA
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
69%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
641 granted / 931 resolved
+0.9% vs TC avg
Strong +26% interview lift
Without
With
+25.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
50 currently pending
Career history
982
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
65.6%
+25.6% vs TC avg
§102
15.9%
-24.1% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of species II, claims 1-9, 11-18 and 20, in the reply filed on March 19, 2026 is acknowledged. Claims 10 and 19 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 19, 2026. Claims 4, 8, 9, 11-18 and 20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species. There is no support in the elected embodiment of Fig. 14 for the claim limitations of "a pair of conductive pillars … on a sidewall of the first lateral stack and on a sidewall of the second lateral stack", as recited in claim 4; “a first plurality of conductive pillars … bordering the first lateral stack on an opposite side of the first lateral stack as the dielectric wall”, as recited in claim 8; and “the first plurality of conductive pillars … border the first lateral stack”, as recited in claim 15, and this feature is found on unelected embodiment of Fig. 15. Information Disclosure Statement The information disclosure statement (IDS) submitted on November 3, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first end of the first lateral stack” and “second end of the first lateral stack” (claim 6) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-3 and 5-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support in the original specification (in the prior-filed application #17/137,768, filed on June 18, 2020) for the claim limitations of "a first lateral stack …, comprises a first channel layer, a first gate layer, and a first ferroelectric layer laterally between the first channel layer and the first gate layer; and a second lateral stack …; wherein the first channel layer, the first gate layer and the first ferroelectric layer form a first memory cell and a second memory cell spaced from each other laterally in the dimension", as recited in claim 1; and “a third lateral stack elongated in the dimension and laterally offset from the first lateral stack”, as recited in claim 5 (note: the specification, i.e. abstract, discloses “the first stacking structure includes first stacking layers …. Each first stacking layer includes a first gate layer, a first channel layer and a first ferroelectric layer between the first gate and channel layers” and paragraph [0073] discloses that “the laterally adjacent memory cells MC in each column of memory cells MC along the direction Y includes two separate, independent channel layers 122”). The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-3 and 5-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claimed limitation of "a first lateral stack elongated in a dimension", as recited in claim 1, is unclear as to a first lateral stack elongated in what dimension(s) applicant refers. The claimed limitation of "the first", as recited in claims 2, 6 and 7, is unclear as to the first of which element applicant refers. The claimed limitation of "second memory cells", as recited in claim 2, is unclear as to whether said limitation is the same as or different from "a second memory cell", as recited in claim 1. The claimed limitation of "second dielectric walls", as recited in claim 6, line 5, is unclear as to whether said limitation is the same as or different from "a second dielectric wall", as recited in claim 6, line 4. The claimed limitation of "second lateral stacks", as recited in claim 7, is unclear as to whether said limitation is the same as or different from "a second lateral stack", as recited in claim 1. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-3 and 5, as best understood, is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (2021/0375932). The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. As for claim 1, Wang et al. show in Figs. 1A-1C, 4 and related text a three-dimensional memory device, comprising: a first lateral stack (2nd one from bottom of) 123A/111A/(a first respective portion of) 113A elongated in a dimension, wherein the first lateral stack comprises a first channel layer 113A, a first gate layer 123A, and a first ferroelectric layer 111A ([0052]) laterally between the first channel layer and the first gate layer; and a second lateral stack (left 3rd one from bottom of) 123A/111A/(a second respective portion of) 113A overlying and spaced from the first lateral stack; wherein the first channel layer, the first gate layer, and the first ferroelectric layer form a first memory cell 101A and a second memory cell 101A spaced from each other laterally in the dimension, and wherein the first gate layer and the first ferroelectric layer are continuous from the first memory cell to the second memory cell. As for claim 1, Wang et al. show an insulator 121 laterally between the first and second memory cells and cutting the first channel layer into discrete segments (Fig. 1A). Regarding the process limitations ("cutting the first channel layer into discrete segments"), these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear. As for claim 3, Wang et al. show the second lateral stack forms a third memory cell 101A overlying the first memory cell and electrically coupled in parallel with the first memory cell (Figs. 1A and 4). As for claim 5, Wang et al. show a third lateral stack (right 3rd one from bottom of) 123A/111A/(a third respective portion of) 113A elongated in the dimension and laterally offset from the first lateral stack, wherein the third lateral stack mirrors the first lateral stack (Figs. 1A and 4). Allowable Subject Matter Claims 6 and 7 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of “a first dielectric wall and a second dielectric wall between which the first lateral stack is laterally sandwiched, wherein the first dielectric wall and the second dielectric wall are elongated in the dimension from the first end to the second end”, as recited in claim 6; and “the insulator layer continuously covers the first channel layer, the first gate layer, and the first ferroelectric layer”, as recited in claim 7. Claims 6 and 7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LYNNE GURLEY can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MEIYA LI/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Nov 03, 2023
Application Filed
Apr 29, 2026
Non-Final Rejection mailed — §102, §112
Jul 14, 2026
Examiner Interview Summary
Jul 14, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
69%
Grant Probability
94%
With Interview (+25.5%)
3y 7m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allowance rate.

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