Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, drawn to methods of manufacturing a semiconductor device drawn to claims 1-15 in the reply filed on 06/10/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guler et al. US 20220399451 .
Regarding claim 1, Guler discloses a method, comprising:
forming first semiconductive sheets over a substrate and arranged in a vertical direction (paragraphs [0053 and 0054] discloses fabricating a stack of nanowires 108 over a bulk substrate, as in figure 2C, and paragraphs [0045-0046] disclose that the nanowire comprises a semiconductor material),
and second semiconductive sheets over the substrate and arranged in the vertical direction (paragraphs [0053 and 0054] discloses fabricating a stack of nanowires 108B over a bulk substrate, as in figure 2C),
wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets (paragraph [0038} discloses that the first stack 108 has a greater number of nanowires than the second stack 108B);
forming first source/drain regions on either side of each of the first semiconductive sheets (paragraph [0031] discloses source/drain regions 118 on either side of the first semiconductor sheets 108, shown in figure 1)
and second source/drain regions on either side on either side of each of the second semiconductive sheets(paragraph [0031] discloses source/drain regions 118 on either side of the second semiconductor sheets 108B, shown in figure 2B );
and forming a first gate around each of the first semiconductive sheets (paragraph [0031 and 0038] discloses wherein a first gate structure 110/112is around the first stack of nanowires 108, see figures 1, 2B),
and a second gate around each of the second semiconductive sheets (paragraph [0031 and 0038] discloses wherein a second gate structure 110/112 is around the second stack of nanowires 108B, see figures 1, 2B),
Regarding claim 2, Guler discloses the method of claim 1, wherein the number of the first semiconductive sheets is 1-3 more than the number of the second semiconductive sheets (paragraph [0034] discloses wherein the number of first semiconductive nanowires 108 is 1 more than the number of second semiconductive nanowires 108B.)
Regarding claim 3, Guler discloses the method of claim 1, further comprising: forming
a first protrusion structure protruding from the substrate and underlying the first semiconductive sheets (paragraph [0031] discloses sub-fin 104, which corresponds to a first protrusion structure underlying the first semiconductor nanowires 108, that is, 104 is between the bulk substrate and the first semiconductor layer stack), and
a second protrusion structure protruding from the substrate and underlying the second semiconductive sheets (paragraph [0038] discloses sub-fin 128, which corresponds to a second protrusion structure underlying the second semiconductor nanowires 108B, that is, 128 is between the bulk substrate and the first semiconductor layer stack), wherein
a top surface of the second protrusion structure is in a higher position than a top surface of the first protrusion structure (see annotated figure 2D below).
Regarding claim 4, Guler discloses the method of claim 3, further comprising:
forming a shallow trench isolation (STI) structure laterally surrounding lower portions of the first and second protrusion structures (paragraph [0031] discloses that the sub-fins are separated by shallow trench isolation structures 106),
PNG
media_image1.png
584
729
media_image1.png
Greyscale
wherein the top surface of the first protrusion structure and a top surface of the STI structure has a first distance (d1) therebetween, and the top surface of the second protrusion structure and the top surface of the STI structure has a second distance (d2) therebetween, the second distance is greater than the first distance (see annotated figure 2D, where d2 is greater than d1).
Regarding claim 5, Guler discloses the method of claim 4, wherein the first distance is l to 40 nm greater than the second distance (Annotated figure 2D above, shows that the difference between the first distance d1 and the second distance d2 is about the same as the width of the sub-fin, while paragraph [0077] states that each fin is approximately 10 nm in width. Therefore, the difference between d1 and d2, at approximately 10 nm, falls within the claimed range of 1 to 40 nm.)
Regarding claim 6, Guler discloses the method of claim 1,wherein a lowermost one of the second semiconductive sheets is vertically offset from a lowermost one of the first semiconductive sheets by a non-zero distance (see annotated figure 2D, where the lowermost, that is the one in the opposite of the marked “up” direction, of the second semiconductor sheets 108B is offset vertically from the lowermost of the first semiconductor sheets 108 by the non-zero distance d2-d1).
Regarding claim 7, Guler discloses the method of claim 6, wherein the non-zero distance is in a range from about 5 to 30 nm. (As described in the rejection of claim 6, the non-zero distance is d2-d1. As described in the rejection of claim 5, the difference between d2 and d1 is approximately 10 nm, which is within the claimed range of 5 -30 nm.)
Regarding claim 8, Guler discloses the method of claim 1, wherein a bottom of the second gate is vertically offset from a bottom of the first gate (paragraph 42 discloses that the first gate electrode 112 is around the first set of nanowires 108, and the second gate electrode 112 is around the second set of nanowires 108B – in figure 2C, it is evident that, due to the offset in the bottoms of the nanowire stacks, the bottoms of the gate electrode stacks are similarly offset due to the gate being formed around them).
PNG
media_image2.png
561
697
media_image2.png
Greyscale
Regarding claim 9, Guler discloses the method of claim 1, wherein a bottom of one of the second source/drain regions is vertically offset from a bottom of one of the first source/drain regions by a non-zero distance (illustrated in annotated figure 2D below, where the vertical offset between the levels of the bottoms of the first and second S/D structures is non-zero).
Regarding claim 10, Guler discloses the method of claim 1, further comprising:
forming a gate spacer over the first semiconductive sheets and on a sidewall of the first gate (gate spacer layer 110/128 is formed over the first conductive sheets and on the side wall of the first gate [0031], figure 1)
forming a dielectric helmet layer over the second semiconductive sheets and covering the second gate ([0041] describes the formation of dielectric layer 132 over the second semiconductor stacks)
wherein a top surface of the dielectric helmet layer is level with a top surface of the gate spacer (the top surface of the gate dielectric 110/128 is level with 132, as seen in figure 3B).
Claims 21 – 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mehandru et al. US 20230317808.
Regarding claim 21, Mehandru discloses a method, comprising:
forming a first transistor over a substrate, the first transistor comprising: a plurality of first nanostructures arranged in a vertical direction (paragraph [0084] and figure 7A disclose formation of a first transistor over the substrate 702 comprising a plurality of first nanowires 706 arranged in a vertical direction) ;
a plurality of first epitaxial structures on either side of each of the first nanostructures (paragraph [0089] and figure 7F disclose the formation of first epitaxial structures 722 and 716 on either side of the first nanostructures 706);
and a first gate structure around the first nanostructures and between the first epitaxial structures (paragraphs [0090] and figure 7H disclose the formation of first gate structures 726/728 around the first nanostructures 406 and between the first epitaxial structures 722 and 716);
forming a second transistor over the substrate, the second transistor comprising: a plurality of second nanostructures arranged in the vertical direction (Paragraph [0034] and figure 1A disclose a layout wherein a second transistor is formed over the same substrate as the first transistor. Paragraph [0094] discloses that the structures of the present embodiment of figures 7A-7J can be formed using this differential channel sizing approach. The second transistor is formed analogously to the first transistor - paragraph [0084] and figure 7A disclose formation of a second transistor over the substrate 702 comprising a plurality of second nanowires 706 arranged in a vertical direction),
wherein a number of the second nanostructures is less than a number of the first nanostructures (paragraph [0036] and figures 1C and 1D disclose that the number of second nanostructures 164 in figure 1D is less than the number of first nanostructures 144 in figure 1C);
a plurality of second epitaxial structures on either side of each of the second nanostructures (analogously to the formation of the first epitaxial structures, paragraph [0089] and figure 7F disclose the formation of second epitaxial structures 722 and 716 on either side of the second nanostructures 706);
and a second gate structure around the second nanostructures and between the second epitaxial structures (paragraphs [0090] and figure 7H disclose the formation of second gate structures 726/728 around the second nanostructures 406 and between the second epitaxial structures 722 and 716);
forming a first metal contact over one of the first epitaxial structures (paragraph [0091] and figure 7J disclose the formation of a first metal contact 734 over one of the first epitaxial structures 734);
and forming a second metal contact over one of the second epitaxial structures, wherein a bottom of the second metal contact is deeper than a bottom of the first metal contact (paragraph [0092] discloses that one of the second metal contact structures 736 in figure 7J may be formed over the second epitaxial structures, where the bottom of the second metal contact 736 is deeper than the bottom of the first metal contact structure 734).
Regarding claim 22, Mehandru discloses the method of claim 21, wherein a vertical dimension of the second metal contact is greater than a vertical dimension of the first metal contact (figure 7J shows that the vertical dimension of the second metal contact is greater than the vertical dimension of the first metal contact).
Regarding claim 23, Mehandru discloses the method of claim 21,wherein a vertical dimension of the one of the second epitaxial structures is less than a vertical dimension of the one of the first epitaxial structures (As described in the rejection to claim 21, the number of second nanosheets is less than the number of first nanosheets. Therefore, as the epitaxial structures are formed at the sides of each of the nanosheets, as described in the rejection of claim 21, as well as the fact that the second layer of nanosheets is shorter, as seen in figures 1C and 1D, means that the second epitaxial structures must have a lesser vertical extent than the first epitaxial structures.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Mehandru et al. US 20230317808.
Regarding claim 11, Mehandru discloses a method, comprising: forming a first device over a substrate, the first device comprising:
a plurality of first channel patterns stacked in a vertical direction (paragraph [0084] and figure 7A disclose formation of a plurality first transistor devices as illustrated in figure 1A, comprising a plurality of first channel patterns of nanowires 706, arranged in a vertical direction) a first gate pattern wrapping around the first channel patterns (paragraphs [0090] and figure 7H disclose the formation of first gate structures 726/728 around the first channel patterns comprising nanowires 406);
and a plurality of first epitaxial patterns on either side of each of the first channel patterns (paragraph [0089] and figure 7F disclose the formation of first epitaxial structures 722 and 716 on either side of the first channel patterns comprising nanostructures 706);
PNG
media_image3.png
523
608
media_image3.png
Greyscale
and forming a second device over the substrate, the second device comprising: a plurality of second channel patterns stacked in the vertical direction (Paragraph [0034] and figure 1A disclose a layout wherein a second transistor is formed over the same substrate as the first transistor. Paragraph [0094] discloses that the structures of the present embodiment of figures 7A-7J can be formed using this differential channel sizing approach. The second transistor is formed analogously to the first transistor - paragraph [0084] and figure 7A disclose formation of a second transistor over the substrate 702 comprising a plurality of second channel patterns 706 arranged in a vertical direction).
wherein a lowermost one of the second channel patterns is in a higher position than a lowermost one of the first channel patterns (see annotated figures, 1C and 1D, where the lowermost of the second channel patterns is in a higher position than the lowermost of the first channel patterns – paragraph [0095] teaches that the structures of the embodiment of figures 7A-7J can be );
a second gate pattern wrapping around the second channel patterns (paragraphs [0090] and figure 7H disclose the formation of second gate structures 726/728 around the second channel patterns comprising nanostructures 406);
and a plurality of second epitaxial patterns on either side of each of the second channel patterns (analogously to the formation of the first epitaxial structures, paragraph [0089] and figure 7F disclose the formation of second epitaxial structures 722 and 716 on either side of the second channel patterns comprising nanostructures 706.)
Mehendru lacks wherein an uppermost one of the second channel patterns is in a lower position than an uppermost one of the first channel patterns.
However, Mehendru discloses in paragraphs [0031- 0033] that nanowire top-down depopulation may, among many other methods, be used to decrease the number of channel patterns in certain transistors in order to increase the differential nanoribbon stack design between memory and logic devices so that the logic devices have smaller capacitance, while the memory devices have larger capacitance to reduce Vmin.
Therefore, it would have been obvious to a person having ordinary skill in the art to use a top-down depopulation method to further reduce the number of second channel patterns in order to increase the differential stack design, in order to optimize Vmin, thereby producing a channel pattern design where an uppermost one of the second channel patterns is in a lower position than an uppermost one of the first channel patterns.
Regarding claim 12, Mehandru, as modified in claim 11 above, discloses the method of claim 11, wherein a number of the second channel patterns is less than a number of the first channel patterns (paragraph [0036] and figures 1C and 1D disclose that the number of second nanostructures 164, and therefore the number of second channel patterns in figure 1D is less than the number of first nanostructures 144, and therefore the number of first channel structures in figure 1C) .
Regarding claim 13, Mehandru, as modified in claim 11 above, discloses the method of claim 11, wherein a bottom of the second gate pattern is in a higher position than a bottom of the first gate pattern (See the rejection of claim 11 above, where Mehendru, as modified, disclosed that a lowermost one of the second channel patterns is in a higher position than a lowermost one of the first channel patterns. Since, in the rejection of claim 11 above, Mehandru teaches that the gate patterns are formed around the respective channel patterns, the combination of these teachings discloses that the bottom of the second gate pattern is in a higher position than the bottom of the first gate pattern, as in figures 1C and 1D.)
Regarding claim 14, Mehandru, as modified in claim 11 above, discloses the method of claim 11, wherein a bottom of one of the second epitaxial patterns is in a higher position than a bottom of one of the first epitaxial patterns (analogously to the rejection of claim 13 above, Mehendru, as modified, disclosed that a lowermost one of the second channel patterns is in a higher position than a lowermost one of the first channel patterns. Since, in the rejection of claim 11 above, Mehandru teaches that the epitaxial patterns are formed around their respective channel patterns, the combination of these teachings discloses a bottom of one of the second epitaxial patterns is in a higher position than a bottom of one of the first epitaxial pattern.)
Regarding claim 15, Mehandru, as modified in claim 11 above, discloses the method of claim 11, further comprising:
forming a first fin strip protruding from the substrate and underlying the first channel patterns (paragraph [0087 discloses the formation of the fin strip as shown in annotated figure 7D), and
PNG
media_image4.png
551
390
media_image4.png
Greyscale
a second fin strip protruding from the substrate and underlying the second channel patterns (the second fin strip is formed analogously to the first fin strip, as described in the rejection of the previous limitation),
wherein a vertical dimension the second fin strip is greater than a vertical dimension of the first fin strip (figures 1C and 1D, illustrating the relative positions of the differentiated first and second fins, discloses that, while the channel patterns of the first fins are longer than those of the second fins, the tops of the fins are at approximately the same height, necessitating that the second fin strips be longer than the first fin strips).
Allowable Subject Matter
Claims 24 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 24, the prior art does not teach or render obvious the method of claim 21, further comprising: forming a contact etch stop layer over the first and second transistors, wherein the first and second metal contacts pass through the contact etch stop layer, an uppermost one of the first nanostructures and the contact etch stop layer has a first distance therebetween, and an uppermost one of the second nanostructures and the contact etch stop layer has a second distance therebetween, the second distance is greater than the first distance, in the combination as claimed.
Claim 25, depends on claim 24, therefore, upon claim 24 being written in independent form, claim 25 would also be allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Sung et al. US 20230402456 (a nanosheet transistor structure with two nanosheet stack GAAFET design), Cheng et al. US 10243054 (integrating standard gate and extended gate nanosheet transistors on the same substrate), Qayyum et al. US 20250113603 (Gate-all-around integrated circuit structures having depopulated channel structures).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights