Prosecution Insights
Last updated: July 17, 2026
Application No. 18/501,653

PATTERNING METHOD AND STRUCTURES RESULTING THEREFROM

Non-Final OA §102§103
Filed
Nov 03, 2023
Priority
Jul 10, 2020 — continuation of 11/848,239
Examiner
WILCZEWSKI, MARY A
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
709 granted / 835 resolved
+24.9% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
34 currently pending
Career history
868
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
64.6%
+24.6% vs TC avg
§102
11.4%
-28.6% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 835 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office action is in response to the filing of this application on 03 November 2023. Claims 1-20 are pending in the application. Claims 1, 9, and 16 are independent. This application is a continuation of application Serial No. 16/925,918, filed on 10 July 2020, now US Patent 11,848,239. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,848,239. Although the claims at issue are not identical, they are not patentably distinct from each other because the pending claims of the instant application are broader in scope than the patented claims. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 16 is rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Li, US 2018/0122806, cited by Applicant on the Information Disclosure Statement (IDS) submitted on 03 November 2023. With respect to claim 16, Li discloses a method of forming a semiconductor device, shown in Figs. 2-12, the method comprising: forming a semiconductor fin 212 protruding from a shallow trench isolation (STI) region 205 (Fins 211 and 212 protrude from the STI region therebetween the fins.), see Fig. 2 and paragraph [0038]; depositing a gate dielectric layer 203 over the semiconductor fin and the STI region 205, see Fig. 2 and paragraph [0036]; depositing a first work function layer 204 over the gate dielectric layer 203, see Fig. 2 and paragraph [0036]-[0040]; forming a first hard mask layer 301/302 over the first work function layer 204, see Fig. 3 and paragraph [0046]; depositing a bottom anti-reflective coating (BARC) layer 401 over the first hard mask layer 301/302, see Fig. 4 and paragraph [0047]; depositing an organic layer 401 over the BARC layer 401, wherein the BARC layer and the organic layer are isolated from the semiconductor fin 212 and the STI region 205 by the first hard mask layer 301/302, see Fig. 4 and paragraph [0047]; performing a first etching process to remove a portion of the first hard mask layer 301/302 and expose a portion of the first work function layer 204, see Figs. 5-8 and paragraphs [0048]-[0051]; and performing a second etching process to remove the exposed portion of the first work function layer 204 and expose a portion of the gate dielectric layer 203, see Fig. 9 and paragraph [0051]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Li, US 2018/0122806, in view of Chen et al., US 2015/0261087, further in view of Furusawa et al., US 2004/0048203, all cited by Applicant on the Information Disclosure Statement (IDS) submitted on 03 November 2023. With respect to claim 1, Li discloses a method, shown in Figs. 2-12,comprising: depositing a gate dielectric layer 203 over a channel region of a semiconductor fin 212, see Fig. 2 and paragraph [0036]; depositing a first work function layer 204 over the gate dielectric layer 203, see Fig. 2 and paragraphs [0036]-[0040]; depositing a first hard mask layer 301/302 over the first work function layer 204, see Fig. 3 and paragraph [0046]; depositing a bottom anti-reflective coating (BARC) layer 401 over the first hard mask layer 301/302, see Fig. 4 and paragraph [0047]; forming a photoresist layer 401, wherein the BARC layer and the photoresist layer 401 are isolated from the channel region by the first hard mask layer 301/302, see Fig. 4 and paragraph [0047]; and etching a portion of the first hard mask layer 301/302 using the BARC layer 401 as a mask, wherein after etching the portion of the first hard mask layer 301/302, a portion of the first work function layer 204 is exposed, see Figs. 5-.8 and paragraphs [0048]-[0051]. Li discloses forming a photoresist mask 401 over the first hard mask layer 301/302, wherein forming the photoresist mask 401 comprises depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer 301/302, see Fog. 4 and paragraph [0047]. Li discloses in paragraph [0047] that the photoresist mask 401 may include a photoresist and the bottom of the photoresist may have a bottom anti reflective coating (BARC). However, Li lacks anticipation of depositing a second hard mask layer over the BARC layer. Chen et al. disclose a photoresist system which includes a BARC layer 105, an hard mask layer 1001 comprising an inorganic material, and an organic photoresist layer 107, see Fig. 10 and paragraphs [0133]-[0138], [0020], and [0041]. The photoresist system of Chen et al. enables the formation of a uniform photoresist layer over the substrate which ensures that subsequent etching can be better controlled, leading to a more efficient manufacturing process capable of making devices with smaller and smaller dimensions. Given the benefits associated with the photoresist system of Chen et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit a second hard mask layer over the BARC layer in the known method of Li. Although Li teaches depositing a first hard mask layer 301/302 over the first work function layer 204, Li lacks anticipation of the first mask layer comprising aluminum oxide. Li discloses that the first hard mask layer 301/302 comprises silicon oxide, see paragraph [0046]. Furusawa et al. disclose that silicon oxide and aluminum oxide are functionally equivalent hard mask materials, see paragraph [0009]. In light of the disclosure of Furusawa et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that aluminum oxide could have been used as the material of hard mask layer 301/302 in the known method of Li, since aluminum oxide is functionally equivalent to silicon oxide as a hard mask material. With respect to claim 2, the method of Li further comprises: etching the exposed portion of the first work function layer 204 using the BARC layer 401 as a mask (see paragraphs [0003], wherein after etching the exposed portion of the first work function layer 204, a portion of the gate dielectric layer 203 is exposed, see Fig. 9 and paragraph [0051]. In paragraph [0003], Li teaches that the photoresist layer 40 (which includes the BARC layer, as disclosed in paragraph [0047] can be removed after removing the exposed portions of the work function layer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the exposed portion of the first work function layer 204 could have been etched in the known method of Li using the BARC layer 401 as a mask to protect the underlying layers from damage caused by the etching step. With respect to claim 4, the method of Li further comprises: after etching the exposed portion of the first work function layer 204, etching remaining portions of the first hard mask layer 301/302, see Figs. 8-10 and paragraphs [0051]-[0052]; and depositing a second work function layer 1101/1201 over remaining portions of the first work function layer 204 and over the exposed portion of the gate dielectric layer 203, see Figs. 11-12 and paragraphs [0054]-[0056]. With respect to claim 5, in the method of Li, the first work function layer 204 is a p-type work function layer (see paragraphs [0036] and [0055]) and the second work function layer 1201 is an n-type work function layer (see paragraph [0056]). With respect to claim 6, in the method of Li, the second work function layer 1101 is a p-type work function layer, see paragraph [0055]. However, Li fails to teach that the first work function layer 204 can be an n-type work function layer. In the method of Li, the first work function layer 204 is a p-type work function layer (see paragraphs [0036] and [0040]) and the second work function layer 1201 is an n-type work function layer (see paragraphs [0055] and [0056]). However, it would have been within the purview of the skilled artisan to deposit the first work function layer 204 as an n-type work function layer and to subsequently remove the n-type work function layer from the PMOS region and to then deposit the p-type work function layer 1101, as shown in Fig. 11. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first work function layer 204 could have been an n-type work function layer. With respect to claim 7, in the method of Li, the first hard mask layer 301/302 has a thickness that is in a range from 8 Å to 20 Å, see paragraph [0046]. With respect to claim 8. In the method of Chen et al., the second hard mask layer 1001 comprises an oxide, see paragraph [0134].. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Li, US 2018/0122806, in view of Chen et al., US 2015/0261087, further in view of Furusawa et al., US 2004/0048203, as applied to claim 2 above, and further in view of Papanu et al., WO 2007/030476, also cited by Applicant on the Information Disclosure Statement (IDS) submitted on 03 November 2023. Li is applied as above. Li discloses that etching the exposed portion of the first work function layer 204 comprises: a wet etch process using a solution comprising de-ionized water, hydrochloric acid (HCl), and hydrogen peroxide (H202), see paragraph [0051]. Although Li discloses that the wet etch process uses a solution comprising de-ionized water, hydrochloric acid (HCl), and hydrogen peroxide (H202), Li does not disclose using ozonated water. It would have been obvious to the skilled artisan that ozonated de-ionized water could have been used in the SC2 cleaning solution of Li, since ozonated de-ionized water provides a sufficiently reactive oxidizing media to leave the substrate surfaces hydrophilic and serves to oxidize any organic contaminants on the substrate surface, see paragraph [0022] of Papanu et al. Claims 9, 12-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Li, US 2018/0122806, in view of Chen et al., US 2015/0261087, cited by Applicant on the Information Disclosure Statement (IDS) submitted on 03 November 2023. With respect to claim 9, Li discloses a method of forming a semiconductor device, shown in Figs. 2-12, the method comprising: forming a semiconductor fin 212 that protrudes from a substrate 200, see Fig. 2 and paragraph [0036]; depositing a gate dielectric layer 203 over the semiconductor fin 212, see Fig. 2 and paragraph [0036] ; forming a first work function layer 204 over the gate dielectric layer 203, see Fig. 2 and paragraphs [0036]-[0040]; depositing a first hard mask layer 301/302 over the first work function layer 204, see Fig. 3 and paragraph [0046]; depositing a bottom anti-reflective coating (BARC) layer 401 over the first hard mask layer 301/302, see Fig. 4 and paragraph [0047]; forming a photoresist layer 401, wherein a first portion of the BARC layer that overlaps the semiconductor fin 212 has a first thickness, and a second portion of the BARC layer that does not overlap the semiconductor fin 212 has a second thickness, wherein the second thickness is greater than the first thickness, see Figs. 4-5 and paragraphs [0047]-[0048]. As shown in Fig. 5 of Li, the portion of the BARC layer which overlaps semiconductor fin 212 is removed and a second portion of the BARC layer that does not overlap semiconductor fin 212 remains over PMOS region. Therefore, the second thickness of the second portion is greater than the first thickness of the first portion. Li discloses forming a photoresist mask 401 over the first hard mask layer 301/302, wherein forming the photoresist mask 401 comprises depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer 301/302, see Fog. 4 and paragraph [0047]. Li discloses in paragraph [0047] that the photoresist mask 401 may include a photoresist and the bottom of the photoresist may have a bottom anti reflective coating (BARC). However, Li lacks anticipation of depositing a second hard mask layer over the BARC layer. Chen et al. disclose a photoresist system which includes a BARC layer 105, an hard mask layer 1001 comprising an inorganic material, and an organic photoresist layer 107, see Fig. 10 and paragraphs [0133]-[0138], [0020], and [0041]. The photoresist system of Chen et al. enables the formation of a uniform photoresist layer over the substrate which ensures that subsequent etching can be better controlled, leading to a more efficient manufacturing process capable of making devices with smaller and smaller dimensions. Given the benefits associated with the photoresist system of Chen et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit a second hard mask layer over the BARC layer in the known method of Li. With respect to claim 12, the method of Li further comprises: patterning the BARC layer 401, see Fig. 5 and paragraph [0048]; etching a portion of the first hard mask layer 301/302 and a portion of the first work function layer 204 to expose a portion of the gate dielectric layer 203, see Figs. 6-9 and paragraphs 0049]-[0052]; and depositing a second work function layer 1101/1201over the exposed portion of the gate dielectric layer, see Figs. 10-12 and paragraphs [0054]-[0056]. With respect to claim 13, in the method of Li, etching the portion of the first hard mask layer 301/302 comprises a wet etch process using alkaline ammonium hydroxide (NH4OH), see paragraph [0049]. . With respect to claim 15, Chen et al. disclose that the second hard mask layer can be removed by a dry etching process which does not remove the overlying photoresist layer 107 or the underlying BARC layer 105, see Figs. 10-11 and paragraphs [0134]-[0138] of Chen et al., Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second hard mask layer 1001 has a high etching selectivity relative to the BARC layer 105 and the photoresist layer 107 in the known method of Chen et al. Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Li, US 2018/0122806, in view of Chen et al., US 2015/0261087, as applied to claim 9 above, further in view of Furusawa et al., US 2004/0048203, also cited by Applicant on the Information Disclosure Statement submitted on 03 November 2023. Li is applied as above. Li fails to teach depositing the first hard mask layer comprises depositing a material that accumulates positive charge on exposed surfaces of the material, as required in dependent claim 10, and of the first hard mask layer comprising aluminum oxide., as required in dependent claim 11. Furusawa et al. disclose that silicon oxide and aluminum oxide are functionally equivalent hard mask materials, see paragraph [0009]. In light of the disclosure of Furusawa et al., it would have been obvious to the skilled artisan that aluminum oxide could be used as the material of hard mask layer 301. Using aluminum oxide as the hard mask layer 301 in the known method of Li would comprise depositing a material that accumulates positive charge on exposed surfaces of the material, as required in dependent claim 10. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Li, US 2018/0122806, in view of Chen et al., US 2015/0261087, as applied to claim 13 above, further in view of Amini et al., US 5,030,590, newly cited. Although Li discloses wet etching the first hard mask layer 301/302 using alkaline ammonium hydroxide (NH4OH), dependent claim 14 requires the alkaline ammonium hydroxide (NH4OH) solution has a temperature in a range of 25° C to 50° C and a concentration in a range of 1 to 10 percent. Amini et al. disclose the etching of a polysilicon layer (first hard mask layer 301/302 comprises polysilicon in the known method of Li, see paragraph [0046]), using alkaline ammonium hydroxide (NH4OH) at a temperature of 40o to 60o C and a concentration the temperatures at which the wet etch process is performed and the concentration of the solution and/or the concentrations of ammonium hydroxide of from 0.5 to 3.0 weight percent, as set forth in claim 10 of the Patent. Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Li, US 2018/0122806, as applied to claim 16 above, further in view of Chen et al., US 2015/0261087. Li is applied as above. Li discloses forming a photoresist mask 401 over the first hard mask layer 301/302, wherein forming the photoresist mask 401 comprises depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer 301/302, see Fog. 4 and paragraph [0047]. Li discloses in paragraph [0047] that the photoresist mask 401 may include a photoresist and the bottom of the photoresist may have a bottom anti reflective coating (BARC). However, Li lacks anticipation of depositing a second hard mask layer over the BARC layer. Chen et al. disclose a photoresist system which includes a BARC layer 105, an hard mask layer 1001 comprising an inorganic material, and an organic photoresist layer 107, see Fig. 10 and paragraphs [0133]-[0138], [0020], and [0041]. The photoresist system of Chen et al. enables the formation of a uniform photoresist layer over the substrate which ensures that subsequent etching can be better controlled, leading to a more efficient manufacturing process capable of making devices with smaller and smaller dimensions. Given the benefits associated with the photoresist system of Chen et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit a second hard mask layer over the BARC layer in the known method of Li. With the respect to claim 18, in the combination of Li and Chen et al., a material of the first hard mask layer 301/302 (oxide, see paragraph [0046] of Li) and a material of the second hard mask layer 1001 (oxide, see paragraph [0134] of Chen et al.) are the same. With respect to claim 19, in the combination of Li and Chen et al., if the material of the first hard mask layer 301/302 and the second hard mask layer 1001 are the same, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first etching process to remove the portion of the first hard mask layer 301/302 would also remove the second hard mask layer 1001. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Li, US 2018/0122806, as applied to claim 16 above, further in view of Furusawa et al., US 2004/0048203. Li is applied as above. Although Li teaches depositing a first hard mask layer 301/302 over the first work function layer 204, Li lacks anticipation of the first mask layer comprising aluminum oxide. Li discloses that the first hard mask layer 301/302 comprises silicon oxide, see paragraph [0046]. Furusawa et al. disclose that silicon oxide and aluminum oxide are functionally equivalent hard mask materials, see paragraph [0009]. In light of the disclosure of Furusawa et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that aluminum oxide could have been used as the material of hard mask layer 301/302 in the known method of Li, since aluminum oxide is functionally equivalent to silicon oxide as a hard mask material. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARY A. WILCZEWSKI Primary Examiner Art Unit 2898 /MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Nov 03, 2023
Application Filed
Jun 12, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+10.1%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
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