The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (2019/0259822) in view of Park et al. (2016/0322453).Regarding claim 1, Jeon et al. teach in figure 15 and related text a display device comprising:
a substrate 110;
a driving transistor 250 on the substrate and comprising a first active layer 130 and a first gate electrode 170;
a first switching transistor 255 comprising a second active layer 135, the second active layer being disposed on a layer that is different from a layer on which the first active layer is positioned, and a second gate electrode 175;
a second switching transistor 260 comprising a third active layer 140, the third active layer being disposed on a layer that is different from the layer on which the second active layer is positioned, and a third gate electrode 180;
a first gate insulating layer 150 between the second active layer 135 and the second gate electrode 175;
a second gate insulating layer 150 between the third active layer 140 and the third gate electrode 180; and
a third gate insulating layer 150 between the first active layer 130 and the first gate electrode 170,
wherein, in an upward direction from the substrate, the first gate electrode 170 is above the first active layer 130, and the third gate electrode 180 is at a higher level than the third active layer 140, and
wherein at least one layer selected from the second active layer 135 of the first switching transistor and the third active layer 140 of the second switching transistor does not overlap the third gate insulating layer 150 in a thickness direction of the display device.
Jeon et al. do not teach that a first distance between the first active layer 130 and the first gate electrode 170 is greater than a second distance between the third active layer 140 and the third gate electrode 180.
Park et al. teach in figure 3 and related text that the gate insulating layer 120, 130 of the driving transistor 115 is greater than the of the gate insulating layer 120 of the first switching transistor 110.
Park et al. and Jeon et al. are analogous art because they are directed to light emitting display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jeon et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the gate insulating layer of the driving transistor greater than the of the gate insulating layer of the first switching transistor, such that a first distance between the first active layer and the first gate electrode is greater than a second distance between the second active layer and the second gate electrode, as taught by Park et al., in Jeon et al.’s device, in order to adjust the current flow in the driving and switching transistors.
Regarding claim 2, Jeon et al. do not teach that a third distance between the second active layer and the second gate electrode is greater than the second distance between the third active layer and the third gate electrode. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a third distance between the second active layer and the second gate electrode is greater than the second distance between the third active layer and the third gate electrode in prior art’s device in order to be able to use the first switching transistor in application which requires high voltage.
Regarding claim 3, Jeon et al. do not teach that the first active layer and the third active layer each comprise an oxide semiconductor, and the second active layer comprises polysilicon.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first active layer and the third active layer each comprise an oxide semiconductor, and the second active layer comprises polysilicon, in prior art’s device in order to adjust the device characteristics, as is well-known in the art, by adjusting the required electron mobility and the on/off ratio of the different transistors according to the requirements of the application at hand.
Furthermore, it is well known in the art that driving transistors have high mobility and thus have low energy consumption and high reliability. On the other hand, switching transistors have a short ON period and maintains a long OFF period (see e.g. Choi 2020/0209697).
Regarding claim 4, Jeon et al. do not teach that the first gate electrode, the first active layer, the third gate electrode, and the third active layer are each at a higher level than the first gate insulating layer. That is, Jeon et al. do not teach that the first switching transistor is closer to the substrate than the second switching transistor and the driving transistor. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the second switching transistor and the driving transistor further from the substrate than the first switching transistor in prior art’s device in order to provide better insulation to the second switching transistor and the driving transistor by forming them further from the substrate.
Regarding claim 5, Jeon et al. teach in figure 15 and related text that the second gate insulating layer 150 is also between the first gate electrode 130 and the first active layer 170.
Regarding claim 6, Jeon et al. teach in figure 15 and related text that the third gate insulating layer 150 is between the second gate insulating layer 150 (part thereof) and the first active layer 170.
Regarding claim 7, Jeon et al. teach in figure 15 and related text that the third gate insulating layer 150 is disposed directly on the second gate insulating layer 150 (part thereof).
Regarding claim 8, Jeon et al. teach in figure 15 and related text that the third gate electrode is spaced apart from the third gate insulating layer 150 (part thereof).
Regarding claim 9, Jeon et al. teach in figure 15 and related text that the second gate insulating layer 150 is on the first active layer 130.
Regarding claim 10, Jeon et al. teach in figure 15 and related text a fourth gate insulating layer 190 on the first gate electrode, wherein the fourth gate insulating layer directly contacts the second gate insulating layer and the third gate insulating layer.
Regarding claim 11, Jeon et al. teach in figure 15 and related text that the fourth gate insulating layer directly contacts the first gate electrode and the third gate electrode.
Regarding claim 12, Jeon et al. teach in figure 15 and related text that an electrode 290 of a capacitor on the fourth gate insulating layer 190 (since capacitance is present between electrodes 290 and 175), wherein the electrode of the capacitor overlaps the first gate electrode.
Regarding claim 13, Jeon et al. teach in figure 15 and related text a light blocking layer 350 between the substrate and the first active layer, wherein the light blocking layer overlaps the first active layer in the thickness direction of the display device.
Regarding claim 14, Jeon et al. teach in figure 15 and related text that at least one layer selected from among the second active layer and the third active layer does not overlap the light blocking layer in the thickness direction of the display device.
Regarding claim 15, Jeon et al. do not teach that the second gate electrode and the light blocking layer are directly on the first gate insulating layer. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the second gate electrode and the light blocking layer are directly on the first gate insulating layer in prior art’s device in order to apply the light blocking layer of the two transistors structure of figure 13 to the three transistors structure of the embodiment of figure 15.
Regarding claim 16, in the combined device, the first distance is greater than a third distance between the second active layer and the second gate electrode.
Regarding claim 17, Park et al. teach in figure 3 and related text that the gate insulating layer 120, 130 of the driving transistor 115 is greater than the of the gate insulating layer 120 of the first switching transistor 110, such that the first distance between the first active layer and the first gate electrode is greater than the third distance between the second active layer and the second gate electrode.
Park et al. does not teach that the first distance between the first active layer and the first gate electrode is in a range of 2.5 times to 3 times greater than the third distance between the second active layer and the second gate electrode.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first distance between the first active layer and the first gate electrode is in a range of 2.5 times to 3 times greater than the third distance between the second active layer and the second gate electrode, as taught by Park et al., in Jeon et al.’s device, in order to adjust the current flow in the driving and switching transistors.
When the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller , 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Applicant can rebut a prima facie case of obviousness based on overlapping ranges by showing unexpected results or the criticality of the claimed range. "The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims . . . . In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range." In re Woodruff , 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP § 716.02 - § 716.02(g) for a discussion of criticality and unexpected results.
It has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Response to Arguments
1. Applicants argue that Jeon does not teach that "wherein at least one layer selected from the second active layer of the first switching transistor and the third active layer of the second switching transistor does not overlap the third gate insulating layer in a thickness direction of the display device,", because “the layer 150 of Jeon (cited for the claimed third gate insulating layer) should extend through and across, and thus should certainly overlap, in the thickness direction of the display device of Jeon, with both the active layer 135 of the transistor 255 of Jeon and the active layer 140 of the transistor 260 of Jeon”.
1. In Jeon, the second active layer 135 of the first switching transistor and the third active layer 140 of the second switching transistor are located under the third gate insulating layer 150 in a thickness direction of the display device. Therefore, the second active layer of the first switching transistor and the third active layer of the second switching transistor does not overlap (i.e. lying over) the third gate insulating layer in a thickness direction of the display device, as required by the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
5/9/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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