DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (claims 1-20) in the reply filed on 3/16/2026 is acknowledged.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 2 is objected to because of the following informalities: in line 7, "an elevation" should be amended to read -a same elevation-. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US 2022/0367399 and Lin hereinafter) in view of Itakura (US 2023/0268310 and Itakura hereinafter).
As to claims 1-3 and 9: Lin discloses [claim 1] a package structure (Fig 1L; 100; [0084]), comprising: a substrate (120; [0026]); a first electronic component (230A; [0065]) over (if the device is flipped over, 230 will be over 120) the substrate (120); a first electrical connector (left 240; [0065]) between the substrate (120) and the first electronic component (230A); and a protective layer (250; [0080]) encapsulating the first electrical connector (240); [claim 2] further comprising a second electrical connector (right 220 on left side of 230A; [0061]) adjacent to the first electrical connector (left 240), the protective layer (250) is partially spaced apart (by area 270 fills between 220 and 250) from the second electrical connector (right 220 on left side of 230A) by a cavity space (cavity space is that occupied by 270 between adjacent 220 and 240; claim doesn’t state that the cavity space is empty or devoid of material), the protective layer (250) comprises a first portion (left sidewall profile of 250) at a first lateral side (left lateral side shown in Figure) of the first electrical connector (left 240) and a second portion (sidewall profile of 250 along a direction perpendicular to that which is shown in the Figure) at a second lateral side (perpendicular side of 240 to what is shown in Figure) of the first electrical connector (left 240) distinct from the first lateral side (left lateral side shown in Figure); [claim 9] further comprising a second electronic component (130A; [0036]) disposed under (when the device is flipped, 130A will be under 230A and 120) the substrate (120), wherein a width of the second electronic component (130A) is greater (as shown in the Figure, 130A is wider than 230A) than a width of the first electronic component (230A).
Lin fails to expressly disclose [claim 1] wherein the protective layer has a first curved lateral surface concave toward the first electrical connector and recessed with respect to a lateral surface of the first electronic component; [claim 2] where the first portion and the second portion have different widths at an elevation; [claim 3] wherein the first portion and the second portion of the protective layer are geometrically distinct from each other.
Itakura discloses in Figs. 5A-5C an underfill material 130 structure that can be formed between a chip 122 and substrate 10 [claim 1] wherein the protective layer (130; [0026] and [0087]) has a first curved lateral surface concave (131x; [0031] and [0093]) and recessed (sidewall 131x is setback with respect to the vertical sidewall of 22; [0032] and [0093]) with respect to a lateral surface (left “x” direction extending vertical sidewall) of the first electronic component (122); [claim 2] where the first portion (131x; [0093]) and the second portion (131y; [0093]) have different widths (width with respect to the left sidewall of 131 at 131x is greater than that of 131 at 131y as 131y is recessed more) at an elevation (e.g. at the middle of the curve in sidewall 131; [0093]-[0094]); [claim 3] wherein the first portion (131x) and the second portion (131y) of the protective layer (130) are geometrically distinct (131x curve has a smaller radius than that of 131y and is thus distinct geometrically) from each other.
As to [claim 1] where the first curved lateral surface is concave toward the first electrical connector, when the concave structure 31 of Itakura is incorporated into the sidewalls of 250 of 230A in Lin, the concave structure 31 will be concave toward the electrical connectors 240.
Given the teachings of Itakura, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lin by employing the well-known or conventional features of underfill fabrication, such as displayed by Itakura, by employing concave curved sidewall surfaces of the underfill in order to reduce the mounting area of the semiconductor chips on the substrate by removing the portions of underfill that extend beyond the chips ([0079]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Itakura as applied to claim 1 above, and further in view of Ofner et al (US 2008/0122053 and Ofner hereinafter).
Lin combined with Itakura discloses further comprising a second electrical connector (right 240; [0065]) between the substrate (120) and the first electronic component (230A), wherein the first electronic component (230A) has an active surface (surface facing 120) facing the substrate (120).
Lin in view of Itakura fail to expressly disclose the active surface comprises a first region exposed by the protective layer, and the first region is between the first electrical connector and the second electrical connector in a cross-sectional view perspective.
Ofner discloses in Fig. 4 an underfill 8 between a chip 2 and a substrate 4 where the chip 2 comprises an active region (surface of 2 facing 4) where the active surface (surface of 2 facing 4; [0023]) comprises a first region (middle area of 2) exposed (by cavity 12; [0026]) by the protective layer (8; [0024]), and the first region (middle area of 2) is between the first electrical connector (left 6; [0023]) and the second electrical connector (right 6; [0023]) in a cross-sectional view perspective.
Given the teachings of Ofner, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lin in view of Itakura by employing the well-known or conventional features of underfill fabrication, such as displayed by Ofner, by employing a void in the underfill/protective layer that exposes the active surface of the chip 2 that faces the substrate 4 in order to reduce the occurrence of delamination between interfaces ([0028]).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Karashima et al (US 2008/0284046 and Karashima hereinafter).
As to claims 10 and 11: Lin discloses [claim 10] a package structure (Fig 1L; 100; [0084]), comprising: a substrate (120; [0026]) having a first surface (bottom surface as shown in the Figure) and a second surface (top surface as shown in the Figure) opposite to the first surface; a first electronic component (230A; [0065]) disposed over (when the device is flipped over, 230A is over 120’s first surface) the first surface (bottom surface as shown in the Figure); a second electronic component (130A; [0036]) disposed under (when the device is flipped over, 130A is under 120’s second surface) the second surface (top surface as shown in the Figure) of the substrate (120); and a protective layer (250; [0080]) between the first electronic component (230A) and the substrate (120).
Lin fails to expressly disclose [claim 10] wherein the protective layer has a cavity space at least partially overlapping a path between the first electronic component and the second electronic component, and the cavity space is configured to reduce transmission of heat generated by the second electronic component and transmitted toward the first electronic component.
Karashima discloses in Figs. 2-3 an underfill/protective layer 14 between a chip 20 and a substrate 21 [claim 10] wherein the protective layer (Fig. 3(c); 14; [0122]) has a cavity space (30 that become voids between adjacent 12/18; [0120]-[0122]); [claim 11] wherein the protective layer (14) is free of fillers (after heating/curing, the layer 14 comprises only the resin material; [0122] and [0125]).
As to where the cavity space at least partially overlapping a path between the first electronic component and the second electronic component, when the void of Karashima is incorporated into Lin, the void will overlap by some amount a vertical line between the first electronic component 230A and the second electronic component 130A.
As to where the cavity space is configured to reduce transmission of heat generated by the second electronic component and transmitted toward the first electronic component, as the void is formed in the same area as claimed and disclosed (between the first and second electronic components) and both are formed of air surrounded by the underfill, the void of Karashima is able to perform the function recited.
Given the teachings of Karashima, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lin by employing the well-known or conventional features of underfill fabrication, such as displayed by Karashima, by employing a void in the underfill/protective layer that exposes the active surface of the chip 20 that faces the substrate 21 in order to use a method to connect the chip and substrate that provides a stable conductive state and reduces costs ([0002]-[0004] and [0020]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Karashima as applied to claim 11 above, and further in view of Itakura.
Although the structure disclosed by Lin in view of Karashima shows substantial features of the claimed invention (discussed in paragraph 12 above), it fails to expressly disclose:
wherein a corner region of a bottom surface of the first electronic component is exposed by the protective layer.
Itakura discloses in Figs. 5A-5C an underfill material 130 structure that can be formed between a chip 122 and substrate 10 wherein a corner region (left or right corner) of a bottom surface of the first electronic component (122; [0089]) is exposed by the protective layer (130; [0092]).
Given the teachings of Itakura, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lin in view of Karashima by employing the well-known or conventional features of underfill fabrication, such as displayed by Itakura, by employing concave curved sidewall surfaces of the underfill in order to reduce the mounting area of the semiconductor chips on the substrate by removing the portions of underfill that extend beyond the chips ([0079]).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Karashima as applied to claim 10 above, and further in view of Cheng et al (US 2021/0118758 and Cheng hereinafter).
As to claims 13 and 14: Lin combined with Karashima discloses [claim 13] further comprising: a first electrical connector (Fig. 1L; 240; [0065]) between the first electronic component (230A) and the substrate (120); and a second electrical connector (125; [0026]) between the second electronic component (130A) and the substrate (120); [claim 14] further comprising an electrical contact (212; [0063]) disposed at a lateral side (left side) of the first electronic component (230A) and horizontally overlapping the first electrical connector (240), wherein a thickness of the electrical contact (212) is greater (as shown in the Figure, 212 is thicker than the thickness of ball 240 at its center above 122b) than the thickness of the second electrical connector (240).
Lin in view of Karashima fail to expressly disclose [claim 13] wherein a thickness of the first electrical connector is less than a thickness of the second electrical connector.
Cheng discloses in Fig. 5A a substrate 242 with a first electronic component 250 on a top surface and a second electronic components 212 on a bottom surface where the first electronic component 250 is connected to the substrate 242 by first electrical connector 252 and the second electronic component 212 is connected to the substrate 242 by the second electrical connected 214 [claim 13] wherein a thickness of the first electrical connector (252; [0060]) is less than (as shown in Fig. 5A, 252 is smaller than 214) a thickness of the second electrical connector (214; [0058]).
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the sizes of the electrical connectors for the respective electronic components in order to provide a package with a desired height and that has sufficient sizes of connectors to allow communication in the device.
Claims 15, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Yim et al (US 2010/0078791 and Yim hereinafter) in view of Tung (US 2002/0179689 and Tung hereinafter).
As to claims 15, 18, and 19: Lin discloses [claim 15] a package structure (Fig. 1L; 100; [0084]), comprising: a substrate (120; [0026]) comprising a first conductive pad (122b; [0028]) and a second conductive pad (122d; [0028]), the second conductive pad (122d) being exposed by a first opening (by being exposed through an opening and recessing of 121a from Fig. 1A; [0027]) of the substrate (120); an electronic component (230A; [0065]) electrically connected (through 240; [0065]) to the first conductive pad (122b); and a protective layer (250; [0080]) between the substrate (120) and the electronic component (230A), wherein the first opening (exposed portion of 122d by opening and recessing of 121a from Fig. 1A) of the substrate (120) is at a first lateral side (left side) of the protective layer (250); [claim 18] further comprising a plurality of electrical contacts (220; [0061]) disposed at the first lateral side (left side) of the protective layer (250); [claim 19] wherein the substrate (120) further comprises a third conductive pad (220 surround the chip, as further indicated by Fig. 5C; [0061]) exposed by a second opening (by being exposed through an opening and recessing of 121a from Fig. 1A; [0027]) of the substrate (120), the second opening of the substrate (120) is at a second lateral side (top side as in Fig. 5C) of the protective layer (250), the second lateral side (top side as in Fig. 5C) is adjacent to the first lateral side (left side as in Fig. 5C).
Lin fails to expressly disclose where [claim 15] a first ratio of a distance between the protective layer and the first opening of the substrate with respect to a distance between the substrate and the electronic component is less than 25; [claim 18] wherein a second ratio of a distance between the electronic component and one of the electrical contacts with respect to the distance between the substrate and the electronic component is less than 35; [claim 19] a second ratio of a distance between the protective layer and the second opening of the substrate with respect to the distance between the substrate and the electronic component is less than 25.
Yim discloses in Figs. 1A and 2A and [0044] that the distance between the dam 280 and the landing pads/second conductive pad 115 (which correspond to all 220 of Lin) is 50-150 microns. Yim also discloses that the width W of the dam 280 is 50 to 100 microns. Yim further discloses in [0044] that the distance between the electrical contacts 115 and the electronic component 200 can be 80 microns.
Therefore, the edge of the protective layer can be 100-250 microns away from the second conductive pad and third conductive pad, which corresponds to the location of the first and second openings of Lin.
The edge of the electrical contact to the electronic component can be 80 microns.
Tung discloses in Fig. 1B that the distance between a substrate 14 and an electronic component 12 can be 80-100 microns, see [0021].
Therefore, the first ratio of the two values for the first and second openings taught by Yim in view of Tung would be in a range of 1 to 3.125.
The second ration of the values taught by Yim in view of Tung would be in a range of 0.8-1.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the distance as taught by Yim and the height taught by Tung such that the ratio of the distance between either the protective layer and the electrical contacts on either lateral side or the distance between the electronic component and the electrical contacts and height between the substrate and electronic component would be within the respective claimed range in order to allow for the device of Lin to have an increased density of second conductive pads by allowing for the pad area to be reduced ([0044] of Yim) by optimizing the distance between the electronic component and the first opening/second conductive pads and to prevent shearing stress experienced by the die ([0021] of Tung) by optimizing the distance between the substrate and the die using routine experimentation.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Yim in view of Tung as applied to claim 15 above, and further in view of Srinivasan et al (US 2023/0086691 and Srinivasan hereinafter).
Lin combined with Yin and Tung disclose further comprising a plurality of electrical contacts (Fig. 1L; 220; [0061]) disposed at the first lateral side (left side) of the protective layer (250).
Lin in view of Yim in view of Tung fail to expressly disclose wherein a second ratio of a distance between the protective layer and one of the electrical contacts with respect to a pitch of the electrical contacts is less than 0.8.
Yim discloses in Figs. 1A and 2A and [0044] that the distance between the dam 280 and the landing pads/second conductive pad 115 is 50-150 microns. Yim also discloses that the width of the dam 280 is 50 to 100 microns. Therefore, the edge of the protective layer is 100-250 microns away from the second conductive pad.
Srinivasan discloses in [0103] that the pitch between package substrate contacts 146 can be between 40 microns and 130 microns.
Therefore, the ratio of the two values taught by Yim in view of Tung in view of Srinivasan would be in a range of 0.77-6.25.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the distance as taught by Yim and the pitch taught by Srinivasan such that the ratio of the distance and pitch would be within the claimed range in order to allow for the device of Lin to have an increased density of second conductive pads by allowing for the pad area to be reduced ([0044] of Yim) by optimizing the distance between the electronic component and the electrical contacts and set the pitch of the contacts in order to maximize the space of the substrate using routine experimentation.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Yim in view of Tung as applied to claim 15 above, and further in view of Wyckoff et al (US 2024/0413111 and Wyckoff hereinafter).
Lin combined with Yin and Tung disclose further comprising a plurality of electrical contacts (Fig. 1L; 220; [0061]) disposed at the first lateral side (left side) of the protective layer (250).
Lin in view of Yim in view of Tung fail to expressly disclose wherein a second ratio of a distance between the protective layer and one of the electrical contacts with respect to a width of the one of the electrical contacts is less than 0.2.
Yim discloses in Figs. 1A and 2A and [0044] that the distance between the dam 280 and the landing pads/second conductive pad 115 is 50-150 microns. Yim also discloses that the width of the dam 280 is 50 to 100 microns. Therefore, the edge of the protective layer is 100-250 microns away from the second conductive pad.
Wyckoff discloses in [0048] that solder balls, such as 220 of Lin, that are formed on a substrate can have a width of 500-900 microns.
Therefore, the ratio of the two values taught by Yim in view of Tung in view of Wyckoff would be in a range of 0.11-0.28.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the distance as taught by Yim and the width taught by Wyckoff such that the ratio of the distance and width would be within the claimed range in order to allow for the device of Lin to have an increased density of second conductive pads by allowing for the pad area to be reduced ([0044] of Yim) by optimizing the distance between the electronic component and the electrical contacts and set the width of the contacts in order to maximize the space of the substrate using routine experimentation.
Allowable Subject Matter
Claims 5-8 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
3/31/2026
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