Prosecution Insights
Last updated: April 19, 2026
Application No. 18/502,103

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §103
Filed
Nov 06, 2023
Examiner
NICELY, JOSEPH C
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
UNITED MICROELECTRONICS CORPORATION
OA Round
5 (Non-Final)
77%
Grant Probability
Favorable
5-6
OA Rounds
2y 4m
To Grant
97%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
603 granted / 781 resolved
+9.2% vs TC avg
Strong +20% interview lift
Without
With
+20.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
37 currently pending
Career history
818
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
49.4%
+9.4% vs TC avg
§102
21.3%
-18.7% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 781 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office action is in response to the RCE filed 2/5/2026 in which claims 1 was amended. Claims 1-14 are pending with claims 8-14 remaining withdrawn and claims 1-7 presented for examination. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 2, and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Jacob et al (US 2020/0098976 and Jacob hereinafter) in view of Bak et al (US 2017/0054070 and Bak hereinafter). As to claims 1, 2, and 4-7: Jacob discloses [claim 1] a semiconductor device (Fig. 13; [0017]), comprising: a magnetic tunneling junction (MTJ) (60; [0028]) on a substrate (Fig. 1; 12; [0017]); a first liner (Fig. 6; 70; [0029]) adjacent to the MTJ (60); wherein sidewalls (inner sidewalls) of the first liner (70), and the MTJ (60) are aligned (inner sidewalls of 70 and outer sidewalls of 60 interface along a plane perpendicular to the substrate top surface and are thus aligned) and perpendicular to a top surface of the substrate (12); and a first metal interconnection (131; [0041]) on the MTJ (60); [claim 2] further comprising: a first inter-metal dielectric (IMD) layer (80; [0033]) around the first liner (70); a second metal interconnection (21; [0019]) under the MTJ (60); and a second IMD layer (Fig. 1; 16; [0019]) around the second metal interconnection (21); [claim 4] wherein a top surface of the MTJ (60) comprises a planar surface (as shown in the Figure); [claim 5] wherein a first sidewall (left sidewall) of the first metal interconnection (131) is aligned with a first sidewall (left sidewall) of the MTJ (60, as disclosed in [0032], opening 91 (Fig. 8) in which 131 is formed is the same width as 60); [claim 6] wherein a second sidewall (right sidewall) of the first metal interconnection (131) is aligned with a second sidewall (right sidewall) of the MTJ (60, as disclosed in [0032], opening 91 (Fig. 8) in which 131 is formed is the same width as 60). Jacob fails to expressly disclose [claim 1] a second liner on and directly contacting the first liner, wherein sidewalls of the first liner and the MTJ and the second liner are aligned and perpendicular to a top surface of the substrate; wherein the first metal interconnection comprises a barrier layer directly contacting the second liner; [claim 2] where the first IMD is around the second liner; [claim 7] wherein the first liner and the second liner are made of different materials. Bak discloses an MTJ device in Fig. 16 with [claim 1] a second liner (205; [0115]) on and directly contacting the first liner (195; [0120]); wherein the first metal interconnection (260; [0125]) comprises a barrier layer (240; [0126]) directly contacting the second liner (205); [claim 2] where the first IMD (220; [0130]) is around the second liner (205); [claim 7] wherein the first liner (195) and the second liner (205) are made of different materials (190/195 can be SiN and 200/205 can be an oxide; [0118] and [0123]). As to [claim 1] wherein sidewalls of the first liner and the MTJ and the second liner are aligned and perpendicular to a top surface of the substrate, when the second liner 205 of Bak is incorporated into the structure of Jacob, 205 will be formed over and on top of 70 in order to contact 131 and will be etched using the opening 91 as the layers of Jacob are thus providing aligned sidewalls of the liners and MTJ that are perpendicular to the substrate top surface. Given the teachings of Bak, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Jacob by employing the well-known or conventional features of MTJ fabrication, such as displayed by Bak, by employing a second liner over the first liner such that it is in direct contact with the barrier layer of the first metal interconnection in order to prevent an electrical short. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jacob in view of Bak as applied to claim 2 above, and further in view of Shum et al (US 2020/0035906 and Shum hereinafter). Although the structure disclosed by Jacob in view of Bak shows substantial features of the claimed invention (discussed in paragraph 8 above), it fails to expressly disclose: wherein a thickness of the first liner on a sidewall of the MTJ is less than the thickness of the first liner on a top surface of the second IMD layer. Shum discloses an MTJ device in Fig. 4 wherein a thickness of the first liner (419; [0041]) on a sidewall of the MTJ (407; [0038]) is less than the thickness of the first liner (419) on a top surface of the second IMD layer (comprising 415 and 417; [0041]). Given the teachings of Shum, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Jacob in view of Bak by employing the well-known or conventional features of MTJ fabrication, such as displayed by Shum, by employing a smaller thickness of the first liner on the MTJ sidewalls compared to the thickness of the first liner on the second IMD layer in order to provide a more cost effective method of forming the device ([0004]). Response to Arguments Applicant’s arguments with respect to claim(s) 1-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JOSEPH C. NICELY Primary Examiner Art Unit 2813 /JOSEPH C. NICELY/Primary Examiner, Art Unit 2813 3/7/2026
Read full office action

Prosecution Timeline

Nov 06, 2023
Application Filed
Apr 08, 2025
Non-Final Rejection — §103
Jun 06, 2025
Response Filed
Jun 27, 2025
Final Rejection — §103
Sep 01, 2025
Request for Continued Examination
Sep 03, 2025
Response after Non-Final Action
Sep 08, 2025
Non-Final Rejection — §103
Nov 05, 2025
Response Filed
Nov 13, 2025
Final Rejection — §103
Jan 13, 2026
Interview Requested
Jan 22, 2026
Examiner Interview Summary
Jan 22, 2026
Applicant Interview (Telephonic)
Feb 05, 2026
Request for Continued Examination
Feb 14, 2026
Response after Non-Final Action
Mar 07, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12588438
LAYER STRUCTURES INCLUDING DIELECTRIC LAYER, METHODS OF MANUFACTURING DIELECTRIC LAYER, ELECTRONIC DEVICE INCLUDING DIELECTRIC LAYER, AND ELECTRONIC APPARATUS INCLUDING ELECTRONIC DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12588255
SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12581961
SUBSTRATE HAVING A DIE POSITION MARK AND A SEMICONDUCTOR DIE STACK STRUCTURE INCLUDING SEMICONDUCTOR DIES STACKED ON THE SUBSTRATE
2y 5m to grant Granted Mar 17, 2026
Patent 12575341
METHOD FOR ANNEALING BONDING WAFERS
2y 5m to grant Granted Mar 10, 2026
Patent 12575160
BACKSIDE AND FRONTSIDE CONTACTS FOR SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

5-6
Expected OA Rounds
77%
Grant Probability
97%
With Interview (+20.1%)
2y 4m
Median Time to Grant
High
PTA Risk
Based on 781 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month