DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Entry of Amendments
Claim(s) 1-6, 10 and 12-19 have been amended.
Objections to the Claims
Amendments made to claim(s) 12 have overcome the previous objection. Claim(s) 12 are no longer objected.
Rejections under 35 USC 102 and 103
Applicant’s amendments filed 11/04/2025 with respect to Claim(s) 1-20 have been fully considered but they are not persuasive.
Applicant's amendments/arguments with respect to Claim(s) 1-20 have been considered but are moot because the arguments do not apply to the reference(s) and/or ground(s) being used in the current rejection.
For further details see the rejections/objections for Claim(s) 1-20 herein.
Claim Objections
Claim 13 is objected to because of the following informalities:
Claim 13 recites a phrase “the second initialization voltage line portions are respectively are arranged in every n pixel columns” in line 3. Examiner suggests amending the phrase to recite “the second initialization voltage line portions are respectively arranged in every n pixel columns” to restore clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 10-14 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over AMATSUCHI et al. (US 20170098398; hereinafter AMATSUCHI) in view of KIM et al. (US 20230200195).
Regarding claim 1, AMATSUCHI teaches in figure(s) 1-8 a method for repairing a display panel, the method comprising:
inspecting a display panel (display panel 1) including pixels (pixels 110; fig. 1) arranging along a first direction and a second direction crossing the first direction (para. 24 - arranged in rows and columns) to detect a defective pixel among the pixels (step S20 in fig. 4; abs. - identifying a defective pixel); and
forming a cut portion through which an initialization voltage (vini; fig. 2) is applied between the defective pixel and pixels (para. 27 - applying various voltages such as an initialization voltage and a reference voltage to the pixels 110),
wherein the defective pixel is isolated, through the cut portion, from the initialization voltage line through which the initialization voltage is applied (para. 3 - By irradiating the non-overlapping portion of the defective pixel with a laser, the non-overlapping portion is cut-off).
AMATSUCHI does not teach explicitly forming a cut portion on an initialization voltage line.
However, KIM teaches in figure(s) 1-14 forming a cut portion (para. 6-7 - Each of the plurality of reference connection lines includes a first laser cutting area disposed between the plurality of subpixels; fig. 9) on an initialization voltage line (REFL; para. 46 - reference line REFL may supply an initialization voltage (or reference voltage) to the driving transistor DTR of each of the subpixels).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of AMATSUCHI by having forming a cut portion on an initialization voltage line as taught by KIM in order to provide combining prior art elements according to known methods to yield predictable results as evidenced by "repair a defective subpixel without loss of an aperture ratio and transmittance… a reference line extended from the non-transmissive area in a first direction, to which a reference voltage is applied, and a plurality of reference connection lines connected to the reference line to transfer the reference voltage to each of the plurality of subpixels. Each of the plurality of reference connection lines includes a first laser cutting area disposed between the plurality of subpixels" (abstract).
Regarding claim 2, AMATSUCHI teaches in figure(s) 1-8 the method of claim 1, wherein: the initialization voltage line is electrically connected to the pixels to apply the initialization voltage (vini; fig. 2); and each of the pixels comprises: a circuit unit including transistors and a capacitor (transistors, capacitor of 110; fig. 2); and a light emitting element (abs. - organic EL element and a drive transistor) electrically connected to the circuit unit, and wherein among the transistors, an initialization transistor includes a semiconductor pattern connected to the initialization voltage line (para. 41 - a line defect in the form of a vertical stripe is visible. This vertical stripe line defect consists of a certain pixel column that emits light at a luminance that does not reflect the data voltage for the inputted display gray level signals).
Regarding claim 3, AMATSUCHI teaches in figure(s) 1-8 the method of claim 2, wherein the initialization voltage line comprises: a first initialization voltage line portion (Vini for pixel 1) formed as a single body with the semiconductor pattern of the initialization transistor (104); and a second initialization voltage line portion (Vini for pixel 2) intersecting the first initialization voltage line portion in a plan view and electrically connected to the first initialization voltage line portion, and wherein the cut portion is formed such that a portion connected to the semiconductor pattern of the initialization transistor of the defective pixel from the first initialization voltage line portion is cut (para. 3 - transmission of electric signals to the defective pixel is blocked).
Regarding claim 4, AMATSUCHI in view of KIM teaches the method of claim 2,
KIM additionally teaches in figs. 1-14 wherein: the semiconductor pattern of the initialization transistor (TR2 in fig. 9) of the defective pixel extends from the initialization voltage line (REFL); and the cut portion (LCA1) is formed such that a portion of the semiconductor pattern (horizontal wiring @ LCA1) of the defective pixel is cut.
Regarding claim 5, AMATSUCHI teaches in figure(s) 1-8 a display panel comprising:
pixel units (pixels 110; fig. 1) arranged along a first direction and a second direction intersecting the first direction (para. 24 - arranged in rows and columns); and
an initialization voltage line (131; para. 37 - a source electrically connected to the drain of the drive transistor 102, and a drain to which an EL anode power supply voltage Vdd is applied) electrically connected to the pixel units to apply an initialization voltage (Vini; para. 27 - applying various voltages such as an initialization voltage and a reference voltage to the pixels 110),
wherein, a cut portion is defined through which the initialization voltage is applied in a first pixel among the pixels (para. 3 - By irradiating the non-overlapping portion of the defective pixel with a laser, the non-overlapping portion is cut-off).
AMATSUCHI does not teach explicitly a cut portion is defined on the initialization voltage line.
However, KIM teaches in figure(s) <fs2num_1> a cut portion (para. 6-7 - Each of the plurality of reference connection lines includes a first laser cutting area disposed between the plurality of subpixels; fig. 9) is defined on the initialization voltage line (REFL; para. 46 - reference line REFL may supply an initialization voltage (or reference voltage) to the driving transistor DTR of each of the subpixels).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of AMATSUCHI by having a cut portion is defined on the initialization voltage line as taught by KIM in order to provide combining prior art elements according to known methods to yield predictable results as evidenced by "repair a defective subpixel without loss of an aperture ratio and transmittance… a reference line extended from the non-transmissive area in a first direction, to which a reference voltage is applied, and a plurality of reference connection lines connected to the reference line to transfer the reference voltage to each of the plurality of subpixels. Each of the plurality of reference connection lines includes a first laser cutting area disposed between the plurality of subpixels" (abstract).
Regarding claim 6, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 5, wherein the initialization voltage line comprises: first initialization voltage line portions extending in the first direction (abs. - a lighted line, which is a pixel column inputted with uniform display gray level signals, and the line defect by displaying the lighted line on the display unit and scanning the display unit with the lighted line in the row direction); and second initialization voltage line portions extending in the second direction crossing the first direction and electrically connected to the first initialization voltage line portions (para. 36 - a source electrically connected to the source of the drive transistor 102, and a drain to which an initialization voltage Vini is applied. The switch 104 switches between application and non-application of the initialization voltage Vini to the second electrode of the capacitor element 107).
Regarding claim 10, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 6, wherein each of the pixels units includes a pixel, and wherein the pixel of each of the pixel units comprises: a circuit unit including transistors and a capacitor (transistors, capacitor of 110; fig. 2); and a light emitting element electrically connected to the circuit unit (abs. - organic EL element and a drive transistor), and wherein an initialization transistor (104) among the transistors includes a semiconductor pattern connected to a corresponding first initialization voltage line portion among the first initialization voltage line portions (para. 36 - switch 104 switches between application and non-application of the initialization voltage Vini to the second electrode of the capacitor element 107).
Regarding claim 11, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 10, wherein the corresponding first initialization voltage line portion (vini) and the semiconductor pattern of the initialization transistor (104) are formed as a single body on the same layer.
Regarding claim 12, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 10, wherein the pixel units includes pixel rows defined by pixel units arranged along the first direction among the pixel units, and the first initialization voltage line portions are respectively arranged along corresponding pixel rows (para. 6 - depending on the defect mode, there are instances where a line (pixel row or pixel column) defect is observed instead of a spot (pixel) defect…precisely observe the pixels included in the line defect one by one to identify the defective pixel to be repaired).
Regarding claim 13, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 12, wherein the pixel units are arranged in pixel columns arranged along the second direction among the pixel units, and the second initialization voltage line portions are respectively arranged in every n pixel columns, where the n is a natural number of 1 or greater (para. 6 - depending on the defect mode, there are instances where a line (pixel row or pixel column) defect is observed instead of a spot (pixel) defect…precisely observe the pixels included in the line defect one by one to identify the defective pixel to be repaired).
Regarding claim 14, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 12, wherein a first initialization voltage line portion among the first initialization voltage line portions is connected to a pixel row including the first pixel among the pixel rows, and wherein the cut portion is formed in the first initialization voltage line portion (para. 8 - performed on the display panel having a line defect which is at least one of a pixel row and a pixel column that emits light at a luminance not reflecting the display gray level signals).
Regarding claim 17, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 12, wherein the initialization transistor of the first pixel comprises a semiconductor pattern extending from a first initialization voltage line portion among the first initialization voltage line portions (Vini for pixel 1), and wherein the cut portion is formed in a portion of the semiconductor pattern of the first pixel, and the first pixel is electrically insulated from the first initialization voltage line portion by the cut portion (para. 3 - separated from other conductive parts and wires, is provided for correcting a defective pixel that has become a bright spot that is always emitting light due to a short circuit).
Regarding claim 18, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 10, wherein the pixels of each of the pixel units comprise: a semiconductor pattern layer including the first initialization voltage line portions (Vini for pixel 1); and a conductive pattern layer disposed on the semiconductor pattern layer and including the second initialization voltage line portions (Vini for pixel 2), and wherein the cut portion is disposed not to overlap the conductive pattern layer in a plan view (para. 3 - transmission of electric signals to the defective pixel is blocked).
Claim(s) 7-9 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over AMATSUCHI in view of KIM, and further in view of Song et al. (US 20230162674).
Regarding claim 7, AMATSUCHI in view of KIM teaches the display panel of claim 6,
AMATSUCHI does not teach explicitly wherein the first initialization voltage line portions and the second initialization voltage line portions are disposed on different layers, respectively.
However, Song teaches in figure(s) 1-15 wherein the first initialization voltage line portions and the second initialization voltage line portions are disposed on different layers, respectively (para. 152 - first gate metal layer to form the gate lines and the gate electrode of each transistor, and a patterning process may be performed on the second gate metal layer to form the second electrode plate of the storage capacitor … the initial data line and the second electrode plate of the storage capacitor may be arranged in a same layer … the initial data line may be formed in the first gate metal layer or the second gate metal layer; fig. 2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of AMATSUCHI by having wherein the first initialization voltage line portions and the second initialization voltage line portions are disposed on different layers, respectively as taught by Song in order to provide "first initialization circuit writes, under the control of a first initialization control signal, an initialization voltage provided by an initialization voltage line, to a control terminal of the driving circuit; the second initialization circuit writes, under the control of a second initialization control signal provided by a second initialization control line, an initial data voltage provided by an initial data line, to an anode of the light-emitting element" (abstract).
Regarding claim 8, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 6,
AMATSUCHI does not teach explicitly wherein the first initialization voltage line portions and the second initialization voltage line portions comprise different materials.
However, Song teaches in figure(s) 1-15 wherein the first initialization voltage line portions and the second initialization voltage line portions comprise different materials (para. 152 - the initial data line may be formed in the first gate metal layer or the second gate metal layer, material).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of AMATSUCHI by having wherein the first initialization voltage line portions and the second initialization voltage line portions comprise different materials as taught by Song in order to provide "A patterning process may be performed on the first gate metal layer to form the gate lines and the gate electrode of each transistor, and a patterning process may be performed on the second gate metal layer to form the second electrode plate of the storage capacitor" (para. 152).
Regarding claim 9, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 8,
AMATSUCHI does not teach explicitly wherein an electrical conductivity of the second initialization voltage line portions is greater than an electrical conductivity of the first initialization voltage line portions.
However, Song teaches in figure(s) 1-15 wherein an electrical conductivity of the second initialization voltage line portions is greater than an electrical conductivity of the first initialization voltage line portions (para. 196 - pattern of the first source and drain metal layer includes first conductive connection portion; its know to have different metal layers with different conductivity).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of AMATSUCHI by having wherein an electrical conductivity of the second initialization voltage line portions is greater than an electrical conductivity of the first initialization voltage line portions as taught by Song in order to provide "Light emission of the light-emitting element from a leakage current and lateral leakage at low gray scales caused when initializing the anode of the light-emitting element can be prevented" (abstract).
Regarding claim 19, AMATSUCHI teaches in figure(s) 1-8 the display panel of claim 6,
AMATSUCHI does not teach explicitly further comprising a driving voltage line extending in the second direction and electrically connected to the pixels of the pixel units to apply a driving voltage, wherein the driving voltage line and the second initialization voltage line portions are disposed on the same layer.
However, Song teaches in figure(s) 1-15 further comprising a driving voltage line extending in the second direction and electrically connected to the pixels of the pixel units to apply a driving voltage, wherein the driving voltage line and the second initialization voltage line portions are disposed on the same layer (para. 152 - patterning process may be performed on the second gate metal layer to form the second electrode plate of the storage capacitor; the initial data line and the gate electrode of each transistor may be arranged in a same layer and made of a same material; fig. 2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of AMATSUCHI by having further comprising a driving voltage line extending in the second direction and electrically connected to the pixels of the pixel units to apply a driving voltage, wherein the driving voltage line and the second initialization voltage line portions are disposed on the same layer as taught by Song in order to provide "initial data line and the gate electrode of the driving transistor are in a same layer and are made of a same material, or, the initial data line and a second electrode plate of the storage capacitor are in a same layer and are made of a same material" (para. 29).
Regarding claim 20, AMATSUCHI in view of Song teaches the display panel of claim 19,
Song additionally teaches in figure(s) 1-15 wherein the driving voltage line (11; fig. 2) is arranged spaced apart from the second initialization voltage line portions (14) in the first direction.
Allowable Subject Matter
Claim(s) 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15, the prior arts of record do not fairly teach or suggest “wherein the cut portion comprises a first cut portion which is formed by cutting a first portion of the first initialization voltage line, and a second cut portion which is formed by cutting a second portion of the first initialization voltage line portion, and wherein an isolated portion of the first initialization voltage line positioned between the first cut portion and the second cut portion is connected to the first pixel.” including all of the limitations of the base claim and any intervening claims.
Claim(s) 16 are objected for dependent upon claim 15.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JUDY NGUYEN can be reached on 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/
Primary Examiner, Art Unit 2858
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