Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to application 18/502377 filed on 11/06/23.
Summary of claims
Claims 1-20 are pending.
Claims 1-20 are rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito et al. (US Pub. 2019/0211475).
As to claim 1 the prior art teaches a method for designing an integrated circuit, comprising:
generating a schematic of an integrated circuit that includes a plurality of components, each of the plurality of components associated with a format, the format indicating a matching group that represents a respective circuit functionality (see fig 1-2 paragraph 0038-0044);
generating a plurality of first device array layouts for the plurality of components, respectively, based on their respective matching groups (see fig 2-6 paragraph 0044-0048);
merging a first subset of the plurality of first device array layouts to form a second device array layout, in response to detecting that the first subset of the first device array layouts share a same first matching group (see fig 2-7 paragraph 0047-0052);
generating a first layer enclosing the second device array layout (see fig 6-10 paragraph 0053-0057);
merging a second subset of the plurality of first device array layouts to form a third device array layout, in response to detecting that the second subset of the first device array layouts share a same second matching group, the second matching group different from the first matching group (see fig 6-10 paragraph 0058-0064);
generating a second layer enclosing the third device array layout (see fig 6-12 paragraph 0063-0068);
merging the second device array layout and the third device array layout to form a fourth device array layout, in response to detecting that the second device array layout and the third device array layout share a same cell type (see fig 7-13 paragraph 0068-0074);
forming a third layer enclosing the fourth device array layout (see fig 8-14 paragraph 0073-0078);
and inserting dummy patterns surrounding the third layer (see fig 9-14 paragraph 0083-0088).
As to claim 2, 10 and 20 the prior art teaches wherein the matching group includes one of: a current mirror, a differential pair, a biasing circuit, a distributed biasing circuit, or a clock sensitive circuit (see fig 1-2 paragraph 0039-0046).
As to claim 3 and 11 the prior art teaches wherein the second device array layout is located immediately next to the third device array layout (see fig 6-10 paragraph 0052-0055).
As to claim 4, 12 and 20 the prior art teaches further comprising determining a dimension of the dummy patterns based at least on a set of system design rule constraints (see fig 8-13 paragraph 0084-0090).
As to claim 5 and 13 the prior art teaches further comprising determining a dimension of the dummy patterns based at least on a dimension of the third layer (see fig 8-13 paragraph 0088-0094).
As to claim 6 and 14 the prior art teaches wherein the cell type includes at least one of: a cell identification, a channel length, a threshold voltage, or a width of an active region (see fig 6-10 paragraph 0059-0064).
As to claim 7 the prior art teaches further comprising inserting a guard ring further surrounding the dummy patterns (see fig 6-10 paragraph 0063-0067).
As to claim 8 the prior art teaches further comprising:
prior to generating the first device array layouts, performing a first Simulation Program with Integrated Circuit Emphasis (SPICE) simulation on the schematic of the integrated circuit (see fig 8-12 paragraph 00103-0107);
verifying the fourth device array layout through at least one of: Layout Versus Schematic (LVS) check, a Layout Parasitic Extraction (LPE) check, or a Design Rule Check (DRC) (see fig 8-12 paragraph 0108-0112);
and selectively performing, based on a result of the verification, a second SPICE simulation on the schematic of the integrated circuit (see fig 8-12 paragraph 0113-0117).
As to claim 9 the prior art teaches a system for designing an integrated circuit, comprising: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to:
generate a schematic of an integrated circuit that includes a plurality of components, each of the plurality of components associated with a format, the format indicating a matching group that represents a respective circuit functionality (see fig 1-2 paragraph 0038-0044);
merge a first device array layout, which corresponds to a first subset of the plurality of components that share a first matching group (see fig 2-7 paragraph 0047-0052), and a second device array layout (see fig 6-10 paragraph 0053-0057), which corresponds to a second subset of the plurality of components that share a second matching group, to form a third device array layout, in response to detecting that the first device array layout and the second device array layout share a same cell type (see fig 6-10 paragraph 0058-0064);
form a first layer enclosing the third device array layout (see fig 7-13 paragraph 0068-0075);
insert dummy patterns surrounding the first layer (see fig 8-14 paragraph 0074-0079);
and insert a guard ring further surrounding the dummy patterns (see fig 9-14 paragraph 0083-0088).
As to claim 15 the prior art teaches wherein each of the first subset of the components and/or each of the second subset of the components includes a plurality of transistors stacked on top of one another (see fig 8-11 paragraph 0076-0081).
As to claim 16 the prior art teaches wherein, in the third device array layout, the first subset of the components and the second subset of the components are interleaved with one another (see fig 8-12 paragraph 00120-0124).
As to claim 17 the prior art teaches wherein the system is further caused to: generate a second layer enclosing the first device array layout; extend the second layer in a first lateral direction until the guard ring is reached; generate a third layer enclosing the second device array layout; and extend the third layer in a second lateral direction until the guard ring is reached (see fig 8-13 paragraph 0128-0134).
As to claim 18 the prior art teaches computer readable medium comprising computer executable instructions for carrying out a method for designing an integrated circuit, the method comprising:
generating a schematic of an integrated circuit that includes a plurality of components, each of the plurality of components associated with a format, the format indicating a matching group that represents a respective circuit functionality (see fig 1-2 paragraph 0038-0044);
merging a first device array layout, which corresponds to a first subset of the plurality of components that share a first matching group (see fig 2-7 paragraph 0047-0052), and a second device array layout (see fig 6-10 paragraph 0053-0057), which corresponds to a second subset of the plurality of components that share a second matching group, to form a third device array layout, in response to detecting that the first device array layout and the second device array layout share a same cell type (see fig 6-10 paragraph 0058-0064);
forming a first layer enclosing the third device array layout (see fig 7-13 paragraph 0068-0075);
inserting dummy patterns surrounding the first layer (see fig 8-14 paragraph 0074-0079);
and inserting a guard ring further surrounding the dummy patterns (see fig 9-14 paragraph 0083-0088).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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