DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner notes that in the response filed 3/12/2026, claims 1 and 14 were amended, claims 18-20 were cancelled, and claims 21-23 were added.
Claims 1-17 and 21-23 are pending and presented for examination.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-17 and 21-23) in the reply filed on 3/12/2026 is acknowledged.
Claim Objections
Claim 14 is objected to because of the following informalities: in line 3, "first sacrificial" should be amended to read -sacrificial-. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-17, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US 2021/0082802 and Huang hereinafter) in view of Kao et al (US 2015/0262860 and Kao hereinafter).
As to claims 1 and 3-13: Huang discloses [claim 1] a method for manufacturing an interconnect structure (Figs. 1A-1K and 3A-3C; [0012]), comprising: forming sacrificial portions (Fig. 1E; 140’; [0057]) and electrically conductive portions (comprising 130’ ; [0056]) on a base structure (comprising 126, 124, 120, 119, 118, 116, 114, 108, 106, 103, and 102; [0014]-[0040]) such that the sacrificial portions (140’) are disposed to alternate with the electrically conductive portions (comprising 130’ ) in a first direction (horizontal direction), and such that the sacrificial portions (140’) and the electrically conductive portions (comprising 130’ ) are elongated in a second direction (vertical direction) transverse to the first direction (horizontal direction); forming blocking portions (Fig. 1I; 150; [0067]-[0068]) respectively on the sacrificial portions (140’); forming a sacrificial layer (Fig. 1K; 156; [0076]) to cover the electrically conductive portions (comprising 130’ ) and the blocking portions (150); forming an electrically conductive via (Fig. 3C; comprising 162 and 164; [0083] and [0093]) which extends through the sacrificial layer (156) so as to permit the electrically conductive via (comprising 162 and 164) to be electrically connected to one of the electrically conductive portions (middle 130’ ); [claim 3] wherein the blocking portions (Fig. 1I; 150) include metal oxide, metal nitride, metal oxynitride, or combinations thereof (150 can comprise an oxide of the listed metals or another metal oxide; [0068]); [claim 4] wherein before performing the removal process, the electrically conductive via (Fig. 3C; comprising 162 and 164) includes a first bottom portion (comprising 162 (and 164 thereon) directly contact the top surface of middle 130’ ) which is disposed on the one of the electrically conductive portions (middle 130’ ), and a second bottom portion (comprising 162 (and 164 thereon) directly in contact with the top surface 152 which is on 150, and thus this portion of 162 and 164 is on (interpreted to mean over) 150) which is disposed on (interpreted to mean over) one of the blocking portions (right 150) that is located next to the one of the electrically conductive portions (middle 130’ ); [claim 5] wherein before performing the removal process, a bottom surface of the electrically conductive via (Fig. 3C; comprising 162 and 164) has a first horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of middle 130’ ) which is located at an upper surface (top surface) of the one of the electrically conductive portions (middle 130’ ), a second horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of 152) which is located at (interpreted to mean near) an upper surface of one of the blocking portions (right 150) that is located next to the one of the electrically conductive portions (middle 130’ ), and an interconnecting region (vertical portion of 162 (and 164 thereon) directly contacting the left vertical sidewall of each of the right 150 and 152) interconnecting the first horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of middle 130’ ) and the second horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of 152); [claim 6] wherein the second horizontal region (Fig. 3C; portion of 162 (and 164 thereon) directly contacting the top surface of 152) is located at a level higher than (relative to the top surface of 130’ ) a level of the first horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of middle 130’); [claim 7] further comprising forming capping portions (Fig. 1E; 138’; [0052] and [0057]), each of which is disposed to separate one of the sacrificial portions (140’) from the base structure (comprising 126, 124, 120, 119, 118, 116, 114, 108, 106, 103, and 102) and two corresponding adjacent ones of the electrically conductive portions (comprising 130’ ); [claim 8] wherein the capping portions (Fig. 1E; 138’) include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbon nitride, silicon oxycarbon nitride, metal oxide, metal nitride, metal oxynitride, or combinations thereof (138 can comprise silicon oxide, etc.; [0052]), the capping portions (138’) being made of a material different (138’ is a dielectric material comprising silicon; [0052]) from a material of the blocking portions (150 is a metal oxide; [0068]); [claim 9] wherein before forming the blocking portions (Fig. 1H; 150), each of the capping portions (Fig. 1F; 138’) has two end surfaces (end surfaces that are co-planar with the top surface of 140’) exposed from a corresponding one of the sacrificial portions (140’), and each of the blocking portions (Fig. 1H; 150) is further formed on the two end surfaces (end surfaces that are co-planar with the top surface of 140’) of a corresponding one of the capping portions (138’); [claim 10] wherein formation of the capping portions (Figs. 1B-1E; 138’), the sacrificial portions (140’) and the electrically conductive portions (comprising 130’ ) includes forming an electrically conductive layer (Fig. 1B; 130 ; [0043]) on the base structure (comprising 126, 124, 120, 119, 118, 116, 114, 108, 106, 103, and 102), patterning the electrically conductive layer (Fig. 1C; 130 becomes 130’; [0048]) to form the electrically conductive portions (130’) and recesses (136; [0048]), each of the recesses (136) being formed between two adjacent ones of the electrically conductive portions (130’), forming a capping layer (Fig. 1D; 138; [0050]) along an upper surface of each of the electrically conductive portions (130’) and along an inner surface of each of the recesses (136), forming a preformed layer (140; [0053]) on the capping layer (138) to fill the recesses (136), and performing a planarization process (Fig. 1E; CMP is the planarization process; [0056]) to expose the upper surface (the upper surface of 130’ is exposed immediately after the planarization process and then the layer 141 is formed thereon; [0056]) of each of the electrically conductive portions (130’), such that the capping layer (138) is formed into the capping portions (138’), and such that the preformed layer (140) is formed into the sacrificial portions (140’); [claim 11] wherein formation of the blocking portions (150) includes forming masking portions (Fig. 1G; 142; [0061]) respectively on (interpreted to mean over) the electrically conductive portions (130’), forming the blocking portions (Fig. 1H; 150; [0067]) respectively on the sacrificial portions (140’), and removing the masking portions (Fig. 1J; [0072]) after forming the blocking portions (150); [claim 12] further comprising forming glue portions (Figs. 1B-1C; 128’; [0041] and [0048]), each of which is disposed between the base structure (comprising 126, 124, 120, 119, 118, 116, 114, 108, 106, 103, and 102) and a corresponding one of the electrically conductive portions (130’); [claim 13] wherein the glue portions (128’) includes titanium, tantalum, titanium nitride, tantalum nitride, or combinations thereof (128 can be TiN, Ti, TaN, or Ta; [0042]).
Huang fails to expressly disclose [claim 1] after formation of the electrically conductive via, performing a removal process to remove the sacrificial layer, the blocking portions and the sacrificial portions so as to form a cavity; and forming a dielectric portion to fill the cavity.
Huang discloses forming an interconnect structure over a base structure comprising semiconductor devices.
Kao discloses a process to improve an interconnect structure over a base structure comprising semiconductor devices ([0002] and [0008]-[0009]). In the process of Kao in Fig. 9 and [0015]-[0026], after providing the conductive features 214 (the claimed electrically conductive portions) and the interleaving dielectric regions 410 (the claimed sacrificial portions), an overlying dielectric layer 510 (the claimed sacrificial layer) in which a metal plug 610 (the claimed electrically conductive via) is formed. Thereafter, the sacrificial layer 510 is removed to expose the top surface of the sacrificial portions 410 (Fig. 10 and [0027]) followed by the removal of the sacrificial portions 410 (Fig. 11 and [0028]) to provide a cavity 710. The cavity is then filled with a dielectric structure comprising 810 and 820 (the claimed dielectric portion; Fig. 12 and [0029]).
Applying the process of Kao to Huang would result in not only the layers 156 (the sacrificial layer) and 140’ (the sacrificial portions) being removed but also 152 and 150 (the blocking portion) so as to expose the sacrificial portions 140’ to be removed.
Therefore, given the teachings of Kao, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Huang by employing the well-known or conventional features of interconnect structure fabrication, such as displayed by Kao, by employing a process to remove previously formed sacrificial portions, blocking layers, and a sacrificial layer around a formed electrically conductive via and then refill with a dielectric structure in order to improve VIMB and TDDB performance and reduction of capacitance of the metal line in the interconnect structure ([0031]).
As to claims 14-17: Huang discloses [claim 14] a method for manufacturing an interconnect structure (Figs. 1A-1K and 3A-3C; [0012]), comprising: forming first sacrificial portions (Fig. 1E; 140’; [0057]) and electrically conductive portions (comprising 130’ ; [0056]) on a base structure (comprising 126, 124, 120, 119, 118, 116, 114, 108, 106, 103, and 102; [0014]-[0040]) such that the sacrificial portions (140’) are disposed to alternate with the electrically conductive portions (comprising 130’ ) in a first direction (horizontal direction), and such that the sacrificial portions (140’) and the electrically conductive portions (comprising 130’ ) are elongated in a second direction (vertical direction) transverse to the first direction (horizontal direction); forming a sacrificial layer (Fig. 1K; 156; [0076]) to cover the sacrificial portions (140’) and the electrically conductive portions (comprising 130’ ); forming an electrically conductive via (Fig. 3C; comprising 162 and 164; [0083] and [0093]) which extends through the sacrificial layer (156) so as to permit the electrically conductive via (comprising 162 and 164) to be electrically connected to one of the electrically conductive portions (middle 130’ ); [claim 15] further comprising forming an etch stop layer (Fig. 1K; 154; [0073]) to cover the electrically conductive portions (130’) and the sacrificial portions (140’) before forming the sacrificial layer (156), the sacrificial layer (156) being formed on the etch stop layer (154), the electrically conductive via (Fig. 3C; comprising 162 and 164) being formed to further extend through the etching stop layer (154) so as to permit the electrically conductive via (comprising 162 and 164) to be electrically connected to the one of the electrically conductive portions (middle 130’); [claim 16] wherein the etch stop layer (Fig. 1K; 154) includes silicon oxycarbide, silicon nitride, silicon carbon nitride, silicon oxycarbon nitride, metal oxide, metal nitride, metal oxynitride, or combinations thereof (154 can be a metal oxide; [0075]); [claim 17] wherein formation of the electrically conductive via (Fig. 3C; comprising 162 and 164) includes patterning the sacrificial layer and the etch stop layer (Fig. 3B; 156 and 154, respectively; [0091]-[0092]) to form a hole (158; [0092]), and forming the electrically conductive via (comprising 162 and 164) in the hole (158).
Huang fails to expressly disclose [claim 14] after formation of the electrically conductive via, performing a removal process to remove the sacrificial layer and the sacrificial portions so as to form a cavity; and forming a dielectric portion to fill the cavity; [claim 15] the etching stop layer being removed during the removal process
Huang discloses forming an interconnect structure over a base structure comprising semiconductor devices.
Kao discloses a process to improve an interconnect structure over a base structure comprising semiconductor devices ([0002] and [0008]-[0009]). In the process of Kao in Fig. 9 and [0015]-[0026], after providing the conductive features 214 (the claimed electrically conductive portions) and the interleaving dielectric regions 410 (the claimed sacrificial portions), an overlying dielectric layer 510 (the claimed sacrificial layer) in which a metal plug 610 (the claimed electrically conductive via) is formed. Thereafter, the sacrificial layer 510 is removed to expose the top surface of the sacrificial portions 410 (Fig. 10 and [0027]) followed by the removal of the sacrificial portions 410 (Fig. 11 and [0028]) to provide a cavity 710. The cavity is then filled with a dielectric structure comprising 810 and 820 (the claimed dielectric portion; Fig. 12 and [0029]).
Applying the process of Kao to Huang would result in not only the layers 156 (the sacrificial layer) and 140’ (the sacrificial portions) being removed but also the etch stop layer 154 so as to expose the sacrificial portions 140’ to be removed.
Therefore, given the teachings of Kao, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Huang by employing the well-known or conventional features of interconnect structure fabrication, such as displayed by Kao, by employing a process to remove previously formed sacrificial portions, etch stop layer, and a sacrificial layer around a formed electrically conductive via and then refill with a dielectric structure in order to improve VIMB and TDDB performance and reduction of capacitance of the metal line in the interconnect structure ([0031]).
As to claims 21-23: Huang discloses [claim 21] a method for manufacturing an interconnect structure (Figs. 1A-1K and 3A-3C; [0012]), comprising: forming a first electrically conductive portion (comprising middle 130’; [0056]) and a second electrically conductive portion (comprising right 130’; [0056]) such that the first electrically conductive portion (comprising middle 130’) and the second electrically conductive portion (comprising right 130’) are spaced apart from each other; forming an electrically conductive via (Fig. 3C; comprising 162 and 164; [0083] and [0093]) so as to permit the electrically conductive via (comprising 162 and 164) to be electrically connected to the first electrically conductive portion (comprising middle 130’), the electrically conductive via (comprising 162 and 164) having a stepwise bottom surface (over middle 130’), a first horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of middle 130’) of the stepwise bottom surface being located at the first electrically conductive portion (middle 130’); [claim 23] wherein the stepwise bottom surface of the electrically conductive via (Fig. 3C; comprising 162 and 164 over middle 130’) further has a second horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of 152) that is spaced apart (vertically separated) from the first electrically conductive portion (middle 130’), and an interconnecting region (vertical portion of 162 (and 164 thereon) directly contacting the left vertical sidewall of each of the right 150 and 152) interconnecting the first horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of middle 130’) and the second horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of 152), the second horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of 152) being located at a level higher than (relative to the top surface of 130’) a level of the first horizontal region (portion of 162 (and 164 thereon) directly contacting the top surface of middle 130’).
Huang discloses [claim 21] after formation of the first electrically conductive portion, the second electrically conductive portion and the electrically conductive via, forming a dielectric portion such that the first electrically conductive portion and the second electrically conductive portion are disposed in a lower part of the dielectric portion, and such that the electrically conductive via is disposed in an upper part of the dielectric portion; [claim 22] wherein the lower part and the upper part of the dielectric portion are made of a same material.
Huang discloses forming an interconnect structure over a base structure comprising semiconductor devices.
Kao discloses a process to improve an interconnect structure over a base structure comprising semiconductor devices ([0002] and [0008]-[0009]). In the process of Kao in Fig. 9 and [0015]-[0026], after providing the conductive features 214 (the claimed first and second electrically conductive portions) and the interleaving dielectric regions 410, an overlying dielectric layer 510 in which a metal plug 610 (the claimed electrically conductive via) is formed. Thereafter, the sacrificial layer 510 is removed to expose the top surface of the sacrificial portions 410 (Fig. 10 and [0027]) followed by the removal of the sacrificial portions 410 (Fig. 11 and [0028]) to provide a cavity 710. The cavity is then filled with a dielectric structure comprising 810 and 820 (the claimed dielectric portion; Fig. 12 and [0029]). The dielectric materials comprising 810 and 820 are both formed in an upper part (formed around 610 above 214) of the dielectric portion comprising 810 and 820 and in a lower part (formed around 214) of the dielectric portion comprising 810 and 820.
Applying the process of Kao to Huang would result in not only the layers 156 (the sacrificial layer) and 140’ (the sacrificial portions) being removed but also the etch stop layer 154 so as to expose the sacrificial portions 140’ to be removed.
Therefore, given the teachings of Kao, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Huang by employing the well-known or conventional features of interconnect structure fabrication, such as displayed by Kao, by employing a process to remove previously formed sacrificial portions, etch stop layer, and a sacrificial layer around a formed electrically conductive via and then refill with a dielectric structure in order to improve VIMB and TDDB performance and reduction of capacitance of the metal line in the interconnect structure ([0031]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Kao as applied to claim 1 above, and further in view of Tong et al (US 2024/0027494 and Tong hereinafter).
Although the method disclosed by Huang in view of Kao shows substantial features of the claimed invention (discussed in paragraph 10 above), it fails to expressly disclose:
wherein the sacrificial portions include polyurea, polylactic acid, polycaprolactone, poly(ethylene oxide), polyacrylate, polyvinyl alcohol, poly(methyl methacrylate), or combinations thereof, and the sacrificial layer includes polyurea, polylactic acid, polycaprolactone, poly(ethylene oxide), polyacrylate, polyvinyl alcohol, poly(methyl methacrylate), or combinations thereof.
Huang in view of Kao discloses a semiconductor process using sacrificial layers 410 and 510 that can comprise materials such as silicon oxide that are removed ([0019]).
Tong discloses that in addition to silicon dioxide, poly(methyl methacrylate) (PMMA) can be used as a sacrificial material, see [0071].
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing the sacrificial layers of Kao to be PMMA instead of silicon oxide; if this leads to the anticipated success, in the instant case a material that can be selectively removed without damaging surrounding structures, it is likely the product not of innovation but of ordinary skill.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/ Primary Examiner, Art Unit 2813
5/4/2026
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