DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species B, illustrated in FIG. 3, in the reply filed on 04/13/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, claim 21 line 2 recites “third trench” which lacks proper antecedent basis within the claim or claim 1 upon which it depends and consequently it is unclear whether “third trench” refers to the “third metal trench” or a different trench. For purposes of examination, “third trench” is interpreted as “third metal trench”. Claim 21 line 3 additionally recites “first trench” which is similarly indefinite and is interpreted as “first metal trench”. Claim 21 line 4 additionally recites “fourth trench” which is similarly indefinite and is interpreted as “fourth metal trench”. Claim 21 line 5 additionally recites “second trench” which is similarly indefinite and is interpreted as “second metal trench”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2,6,9-17,21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication Number 2004/0188845 A1 to Iguchi et al., “Iguchi”.
Regarding claim 1, Iguchi discloses an interconnection structure (e.g. FIG. 4), comprising:
a semiconductor substrate (1, ¶ [0007],[0046],[0047]) that is formed with a first metal trench (one of trenches filled with 118 in region 13, see Examiner-annotated figure below) and a second metal trench (one of trenches filled with 118 in region 12, see Examiner-annotated figure below);
a first metal via (one of 119 in region 13, see Examiner-annotated figure below) that is disposed over and connected to the first metal trench;
a second metal via (119 in region 12, see Examiner-annotated figure below) that is disposed over and connected to the second metal trench;
a third metal trench (filled with 118 in region 13, see Examiner-annotated figure below) that is disposed over and connected to the first metal via; and
a fourth metal trench (118 in region 12, see Examiner-annotated figure below) that is disposed over and connected to the second metal via, wherein a thickness of the third metal trench is different from a thickness of the fourth metal trench (since portions of 118 in region 12 protrude downward to upper sidewalls of 119 as pictured).
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Regarding claim 2, Iguchi discloses the interconnection structure according to claim 1, and Iguchi further discloses wherein a top surface of the third metal trench (see Examiner-annotated figure above) is coplanar (as pictured, see Examiner-annotated figure below) with a top surface of the fourth metal trench.
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Regarding claim 6, Iguchi discloses the interconnection structure according to claim 1, and Iguchi further discloses wherein the semiconductor substrate includes:
a first dielectric layer (lowest 3, ¶ [0007]) in which the first metal trench and the second metal trench are formed;
the interconnection structure further comprising a first etch stop layer (lowest 6, ¶ [0007]) disposed over the first dielectric layer (lowest 3),
a second dielectric layer (lowest 5) disposed over the first etch stop layer (lowest 6),
a second etch stop layer (second from bottom 4) disposed over the second dielectric layer (lowest 5), and
a third dielectric layer (second from bottom 3) disposed over the second etch stop layer (second from bottom 4);
wherein the first metal via (119 in region 13, see Examiner-annotated figure above) and the second metal via (119 in region 12, see Examiner-annotated figure above) are disposed in the second dielectric layer (lowest 5);
wherein the third metal trench (118 in region 13, see Examiner-annotated figure above) is disposed in the third dielectric layer (second from bottom 3); and
wherein the fourth metal trench (118 in region 12, see Examiner-annotated figure above and below) has a first portion that is disposed in the third dielectric layer (second from bottom 3), and a second portion that is disposed in the second dielectric layer (lowest 5).
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Regarding claim 9, Iguchi discloses the interconnection structure according to claim 1, and Iguchi further discloses (see Examiner-annotated figure with claim 1 above) wherein the second metal trench is wider than the first metal trench (width being measured laterally and parallel to the substrate), and the fourth metal trench is thicker than the third metal trench (thickness being measured vertically and perpendicular to the substrate).
Regarding claim 10, Iguchi discloses an interconnection structure (e.g. FIG. 4), comprising:
a semiconductor substrate (1, ¶ [0007],[0046],[0047]) that is formed with a first metal trench (one of trenches filled with 118 in region 13, see Examiner-annotated figure below) and a second metal trench (one of trenches filled with 118 in region 12, see Examiner-annotated figure below);
a third metal trench (filled with 118 in region 13, see Examiner-annotated figure below) that is disposed over the semiconductor substrate and that extends (at least partly in cross-section) parallel to a top surface of the semiconductor substrate (1);
a fourth metal trench (118 in region 12, see Examiner-annotated figure below) that is disposed over the semiconductor substrate and that extends (at least partly in cross-section) parallel to the top surface of the semiconductor substrate (1);
a first metal via (one of 119 in region 13, see Examiner-annotated figure below) that extends from the first metal trench to the third metal trench; and
a second metal via (119 in region 12, see Examiner-annotated figure below) that extends from the second metal trench to the fourth metal trench, wherein a distance between a top surface and a bottom surface of the third metal trench is different from a distance between a top surface and a bottom surface of the fourth metal trench (since portions of 118 in region 12 protrude downward to upper sidewalls of 119 as pictured).
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Regarding claim 11, Iguchi discloses the interconnection structure according to claim 10, and Iguchi further discloses wherein the top surfaces of the third metal trench and the fourth metal trench (see Examiner-annotated figure above) are at a same height (as pictured, see Examiner-annotated figure below) relative to the top surface of the semiconductor substrate.
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Regarding claim 12, Iguchi discloses the interconnection structure according to claim 11, and Iguchi further discloses wherein a distance between the top surface of the third metal trench and a top surface of the first metal trench is equal to a distance between the top surface of the fourth metal trench and a top surface of the second metal trench (see Examiner-annotated figure below):
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Regarding claim 13, Iguchi discloses the interconnection structure according to claim 10, and Iguchi further discloses (see Examiner-annotated figure below) wherein the distance between the top surface and the bottom surface of the fourth metal trench is greater (due to extending additionally downward) than the distance between the top surface and the bottom surface of the third metal trench, and the second metal trench is wider than the first metal trench (as pictured, see Examiner-annotated figure below):
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Regarding claim 14, Iguchi discloses an interconnection structure, comprising:
a first interconnection layer (within lowermost 3) that includes a first metal trench feature (118 in region 13, see Examiner-annotated figure below) and a second metal trench feature (118 in region 12, see Examiner-annotated figure below); and
a second interconnection layer (within lowermost 5 and second from bottom 3) that is disposed over the first interconnection layer, and that includes a first metal via feature (one of 119 in region 13, see Examiner-annotated figure below), a second metal via feature (119 in region 12, see Examiner-annotated figure below), a third metal trench feature (filled with 118 in region 13, see Examiner-annotated figure below) and a fourth metal trench feature (118 in region 12, see Examiner-annotated figure below);
wherein the first metal via feature connects the third metal trench feature to the first metal trench feature, and the second metal via feature connects the fourth metal trench feature to the second metal trench feature; and
wherein a thickness of the third metal trench feature is different from a thickness of the fourth metal trench feature (since portions of 118 in region 12 protrude downward to upper sidewalls of 119 as pictured).
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Regarding claim 15, Iguchi discloses the interconnection structure according to claim 14, and Iguchi further discloses wherein a top surface of the third metal trench feature (see Examiner-annotated figure above) is coplanar (as pictured) with a top surface of the fourth metal trench feature.
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Regarding claim 16, Iguchi discloses the interconnection structure according to claim 15, and Iguchi further discloses wherein a distance between the top surface of the third metal trench feature (see Examiner-annotated figure above) and a top surface of the first metal trench feature is equal (see Examiner-annotated figure below) to the top surface of the fourth metal trench feature and a top surface of the second metal trench feature.
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Regarding claim 17, Iguchi discloses the interconnection structure according to claim 14, and Iguchi further discloses wherein the fourth metal trench feature is thicker than the third metal trench feature, and the second metal trench feature is wider than the first metal trench feature (see Examiner-annotated figure below).
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Regarding claim 21 insofar as definite, Iguchi discloses the interconnection structure according to claim 1, and Iguchi further discloses wherein a thickness of a portion of the first metal via (one of 119 in region 13, see Examiner-annotated figure above) that extends between a bottom surface of the third metal trench (filled with 118 in region 13, see Examiner-annotated figure above) and a top surface of the first metal trench (one of trenches filled with 118 in region 13, see Examiner-annotated figure above) is different (see Examiner-annotated figure below) from a thickness of a portion of the second metal via (119 in region 12, see Examiner-annotated figure above) that extends between a bottom surface of the fourth metal trench (118 in region 12, see Examiner-annotated figure above) and a top surface of the second metal trench (one of trenches filled with 118 in region 12, see Examiner-annotated figure above).
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Allowable Subject Matter
Claims 7-8,19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art e.g. Iguchi teaches the combination of metal trenches and metal vias as discussed above. Prior art e.g. U.S. Patent Application Publication Number 2016/0111371 A1 to Peng et al. teaches an interconnection structure (FIG. 2), comprising:
a semiconductor substrate (100, ¶ [0010]) that is formed with a first metal trench (116A, ¶ [0027]) and a second metal trench (116B);
a first metal via (128A) that is disposed over and connected to the first metal trench (116A);
a second metal via (128B) that is disposed over and connected to the second metal trench;
a third metal trench (144A, ¶ [0050]) that is disposed over and connected to the first metal via (128A); and
a fourth metal trench (144B) that is disposed over and connected to the second metal via, wherein a thickness of the third metal trench (144A left side) is different from a thickness of the fourth metal trench (144B on left and right sides),
and generally teaches barrier layers (112 and 114, ¶ [0022],[0023],[0049]).
However, prior art fails to reasonably teach or suggest all of the limitations of claim 7 together with all of the limitations of claim 6 together with all of the limitations of claim 1. Claim 8 is object to insofar as claim 8 depends upon and includes all of the limitations of claim 7.
Claim 19 is objected to for similar reasons to claim 7 and claim 20 is objected to insofar as it depends upon and includes all of the limitations of claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891
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