6Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 10, 13-14, 22, and 36-39 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Hatano (US 20180145007 A1).
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Regarding claim 1, Hatano discloses a power package comprising: a power substrate (Fig. 83A, 21); one or more power devices (Q1 and Q4) arranged on the power substrate; an assembly comprising a top surface (upper surface), first sides (side surface of 21 nearest N and P and opposing side), and second sides (side surface of 21 nearest GT1 and opposing side); power contacts (N and P); and signal contacts (SST1, GT1, SST4 and GT4), wherein the signal contacts are configured on the top surface, in the top surface, and/or to extend from the top surface (shown); and wherein the signal contacts are arranged in a middle section of the top surface between the second sides (see attached figure).
Regarding claim 2, Hatano discloses wherein the signal contacts are arranged in a middle section of the top surface between the first sides (see attached figure above).
Regarding claim 3, Hatano discloses wherein the signal contacts are arranged in a middle section of the top surface between the power contacts (see attached figure above).
Regarding claim 4, Hatano discloses wherein the signal contacts are arranged above the power substrate (Contacts SST1, GT1, SST4 and GT4 are arranged above the upper surface of power substrate 21).
Regarding claim 5, Hatano discloses wherein the power substrate comprises a die attach region (upper surface of 21) where the one or more power devices are arranged on a surface of the power substrate; and wherein the signal contacts are arranged above the die attach region of the one or more power devices (shown).
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Regarding claim 6, Hatano discloses wherein the signal contacts are arranged on a contact lateral axis that extends between the first sides of the power package; and wherein the contact lateral axis is parallel to a lateral center axis of the power package (see attached figure; an axis having both lateral and longitudinal components extending in a lateral direction between the first sides is shown parallel to an arbitrary lateral center axis).
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Regarding claim 10, Hatano discloses wherein the signal contacts are arranged on a longitudinal contact axis that extends between the second sides of the power package; and wherein the signal contacts are arranged adjacent a contact lateral axis (see attached figure; an axis having both lateral and longitudinal components extending between the second sides is shown adjacent to an arbitrary lateral center axis).
Regarding claim 13, Hatano discloses further comprising signal interconnections (261, 264) configured to connect the signal contacts to respective connections on the one or more power devices to provide signals to the one or more power devices (Fig. 83A shows 261 and 264 connected to their respective surface electrode patterns 23D1 and 23D4, which connect to Q1 and Q4; Para. 839 "the surface electrode pattern 23D1 functions as a drain electrode pattern for an upper-arm (High) side device (SiC MOSFET Q1)"; para. 840 "the drain electrode pattern 23D4 is a drain electrode of the SiC MOSFET Q4, and is also a source electrode of the SiC MOSFET Q1").
Regarding claim 14, Hatano discloses wherein the signal interconnections each have a similar length from the signal contacts to the one or more power devices, where a similar length is within 0% - 20% in length (Fig. 83B shows signal interconnections 261 and 264 each having a substantially identical length from each of their respective signal contacts SST1/GT1 and SST4/GT4 to each of their respective power devices Q1 and Q4).
Regarding claim 22, Hatano discloses wherein the signal contacts are configured to implement at least a source kelvin terminal (source sense terminals SST1 and SST4) and a gate terminal (GT1 and GT4).
Regarding claim 36, Hatano discloses a power package comprising: a power substrate (Fig. 83A, 21); one or more power devices (Q1 and Q4) arranged on the power substrate; an assembly comprising a top surface (upper surface), first sides (side surface of 21 nearest N and P and opposing side), and second sides (side surface of 21 nearest GT1 and opposing side); power contacts (N and P); and signal contacts (GT1 and GT4), wherein the power substrate comprises a die attach region (see attached figure) where the one or more power devices are arranged on a surface (upper surface) of the power substrate; and wherein the signal contacts are arranged above the die attach region of the one or more
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power devices (see attached figure).
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Regarding claim 37, Hatano discloses wherein the signal contacts are arranged in a middle section of the top surface between the first sides (see attached figure).
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Regarding claim 38, Hatano discloses wherein the signal contacts are arranged in a middle section of the top surface between the power contacts (see attached figure).
Regarding claim 39, Hatano discloses wherein the signal contacts are arranged above the power substrate (Contacts GT1 and GT4 are arranged above the upper surface of power substrate 21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Hatano (US 20180145007 A1) in view of Smalley (US 20210183846 A1).
Regarding claim 26, Hatano discloses the power package according to claim 1. However, Hatano does not disclose wherein the signal contacts are configured as a receptacle.
On the other hand, Smalley discloses wherein the signal contacts are configured as a receptacle (Fig. 2, 250). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Hatano according to the teachings of Smalley such that the signal contacts would be configured as receptacles, in order to replace pins which protrude and may be damaged during manufacturing, use, transport, etc.
Allowable Subject Matter
Claims 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 71-76 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 17, the prior art of record fails to disclose wherein the power package has an overall gate-loop inductance that is generated based on a construction and configuration of the signal contacts and/or the signal interconnections; and wherein the signal contacts and/or the signal interconnections are constructed and configured to have a similar overall gate-loop inductance, where a similar overall gate-loop inductance is within 0% - 6% in inductance.
Regarding claim 18, the prior art of record fails to disclose wherein the power package has an overall gate-loop inductance that is generated based on a construction and configuration of the signal contacts and/or the signal interconnections; and wherein the signal contacts and/or the signal interconnections are constructed and configured to have a similar overall gate-loop inductance, where a similar overall gate-loop inductance is within 3 nH.
Regarding claim 71, the prior art of record fails to disclose a power package comprising: a power substrate; one or more power devices arranged on the power substrate; an assembly comprising a top surface, first sides, and second sides; power contacts; and signal contacts; and signal interconnections configured to connect the signal contacts to respective connections on the one or more power devices to provide signals to the one or more power devices, wherein the power package has an overall gate-loop inductance that is generated based on a construction and configuration of the signal contacts and/or the signal interconnections; and wherein the signal contacts and/or the signal interconnections are constructed and configured to have a similar overall gate-loop inductance, where a similar overall gate-loop inductance is within 0% - 6% in inductance. Specifically, the prior art does not disclose wherein the power package has an overall gate-loop inductance that is generated based on a construction and configuration of the signal contacts and/or the signal interconnections, and wherein the signal contacts and/or the signal interconnections are constructed and configured to have a similar overall gate-loop inductance, and where a similar overall gate-loop inductance is within 0% - 6% in inductance.
For this reason, claims 72-76 are also allowable as dependents of claim 71.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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