Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 10, 13-14, 22 and 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatano (US 20180145007 A1) in view of Nikitin (US 20230026022 A1).
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Regarding claim 1, Hatano discloses a power package comprising: a power substrate (Fig. 83A, 21); one or more power devices (Q1 and Q4) arranged on the power substrate; an assembly comprising a top surface (upper surface), first sides (side surface of 21 nearest N and P and opposing side), and second sides (side surface of 21 nearest GT1 and opposing side); power contacts (N and P); and signal contacts (SST1, GT1, SST4 and GT4), wherein the signal contacts are configured on the top surface, in the top surface, and/or to extend from the top surface (shown); and wherein the signal contacts are arranged in a middle section of the top surface between the second sides (see attached figure). However, Hatano does not disclose the assembly encloses at least the one or more power devices.
On the other hand, Nikitin discloses an assembly (Fig. 9B, encapsulant body 108) enclosing at least one or more power devices (dies 208). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Hatano in view of Nikitin according to the teachings of Nikitin such that the power devices would be enclosed in an encapsulant body and the signal contacts would be configured to extend from the top surface of the assembly, in order to protect the semiconductor devices and support the signal contacts during manufacturing, use, transport, etc. as is extremely common in the art.
Regarding claim 2, Hatano discloses wherein the signal contacts are in the middle section of the top surface between the first sides (see attached figure above).
Regarding claim 3, Hatano discloses wherein the signal contacts are in the middle section of the top surface between the power contacts (see attached figure above).
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Regarding claim 4, Hatano discloses wherein the signal contacts are arranged above the power substrate (Contacts SST1, GT1, SST4 and GT4 are arranged above the upper surface of power substrate 21) and laterally inward from each of the first sides and second sides (see attached figure).
Regarding claim 5, Hatano discloses wherein the signal contacts are between the first sides and the second sides (first sides are upper and lower side surfaces in above attached figure, second sides are left and right side surfaces in above attached figure); wherein the power substrate comprises a die attach region where the one or more power devices are arranged on a surface of the power substrate; and wherein the signal contacts are arranged above the die attach region of the one or more power devices (upper surface of 21).
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Regarding claim 6, Hatano discloses wherein the signal contacts are between the first sides and the second sides (first sides are upper and lower side surfaces in above attached figure, second sides are left and right side surfaces in above attached figure); wherein the signal contacts are arranged on a contact lateral axis that extends between the first sides of the power package; and wherein the contact lateral axis is parallel to a lateral center axis of the power package (see attached figure below).
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Regarding claim 10, Hatano discloses where the signal contacts are between the first sides and the second sides (see attached figure); wherein the signal contacts are arranged on a longitudinal contact axis that extends between the second sides of the power package; and wherein the signal contacts are arranged adjacent a contact lateral axis (see attached figure below).
Regarding claim 13, Hatano discloses further comprising signal interconnections (261, 264) configured and/or operable to connect the signal contacts to respective connections on the one or more power devices to provide signals to the one or more power devices (Fig. 83A shows 261 and 264 connected to their respective surface electrode patterns 23D1 and 23D4, which connect to Q1 and Q4; Para. 839 "the surface electrode pattern 23D1 functions as a drain electrode pattern for an upper-arm (High) side device (SiC MOSFET Q1)"; para. 840 "the drain electrode pattern 23D4 is a drain electrode of the SiC MOSFET Q4, and is also a source electrode of the SiC MOSFET Q1").
Regarding claim 14, Hatano discloses wherein the signal interconnections each have a similar length from the signal contacts to the one or more power devices, where a similar length is within 0% - 20% in length (Fig. 83B shows signal interconnections 261 and 264 each having a substantially identical length from each of their respective signal contacts SST1/GT1 and SST4/GT4 to each of their respective power devices Q1 and Q4).
Regarding claim 22, Hatano discloses wherein the signal contacts are configured to implement at least a source kelvin terminal (source sense terminals SST1 and SST4) and a gate terminal (GT1 and GT4).
Regarding claim 37, Hatano discloses wherein the signal contacts are arranged in the middle section of the top surface between the first sides (first sides are upper and lower side surfaces in attached figure in claim 1 rejection). However, Hatano does not disclose wherein the assembly comprises a mold compound that surrounds at least the one or more power devices.
On the other hand, Nikitin discloses wherein the assembly comprises a mold compound (Fig. 9B, encapsulant body 108) that surrounds at least the one or more power devices (dies 208). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Hatano according to the teachings of Nikitin such that the assembly would further comprise a mold compound surrounding the power devices, in order to protect the devices from external moisture and debris, as is extremely common in the art.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Hatano (US 20180145007 A1) in view of Nikitin (US 20230026022 A1) as applied to claims 1-6, 10, 13-14, 22, and 37 above, and further in view of Smalley (US 20210183846 A1).
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Regarding claim 26, Hatano discloses wherein the signal contacts are between the first sides and the second sides (see attached figure). However, Hatano does not disclose wherein the signal contacts are configured as a receptacle.
On the other hand, Smalley discloses wherein the signal contacts are configured as a receptacle (Fig. 2, 250). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Hatano in view of Nikitin according to the teachings of Smalley such that the signal contacts would be configured as receptacles, in order to replace pins which protrude and may be damaged during manufacturing, use, transport, etc.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 36 and 38-39 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Hatano (US 20180145007 A1).
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Regarding claim 36, Hatano discloses a power package comprising: a power substrate (Fig. 83A, 21); one or more power devices (Q1 and Q4) arranged on the power substrate; an assembly comprising a top surface (upper surface), first sides (side surface of 21 nearest N and P and opposing side), and second sides (side surface of 21 nearest GT1 and opposing side); power contacts (N and P); and signal contacts (GT1 and GT4), wherein the power substrate comprises a die attach region where the one or more power devices are arranged on a surface of the power substrate; and wherein the signal contacts are arranged on a middle section of the top surface and above the die attach region of the one or more power devices (see attached figure).
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Regarding claim 38, Hatano discloses wherein the signal contacts are arranged in a middle section of the top surface between the power contacts (see attached figure).
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Regarding claim 39, Hatano discloses wherein the signal contacts are above the power substrate (Contacts GT1 and GT4 are arranged above the upper surface of power substrate 21); and wherein the signal contacts are laterally inward from each of the first sides and the second sides (see attached figure).
Allowable Subject Matter
Claims 17-18 and 71-76 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 17, the prior art of record fails to disclose a power package comprising: a power substrate; one or more power devices arranged on the power substrate; an assembly comprising a top surface, first sides, and second sides; power contacts; signal contacts; and signal interconnections configured to connect the signal contacts to respective connections on the one or more power devices to provide signals to the one or more power devices, wherein the signal contacts are configured on the top surface, in the top surface, and/or to extend from the top surface; wherein the signal contacts are arranged in a middle section of the top surface between the second sides; wherein the power package has an overall gate-loop inductance that is generated based on a construction and configuration of the signal contacts and/or the signal interconnections; and wherein the signal contacts and/or the signal interconnections are constructed and configured to have a similar overall gate-loop inductance, where a similar overall gate-loop inductance is within 0% - 6% in inductance. Specifically, the prior art of record fails to disclose wherein the power package has an overall gate-loop inductance that is generated based on a construction and configuration of the signal contacts and/or the signal interconnections; and wherein the signal contacts and/or the signal interconnections are constructed and configured to have a similar overall gate-loop inductance, where a similar overall gate-loop inductance is within 0% - 6% in inductance.
Regarding claim 18, the prior art of record fails to disclose a power package comprising: a power substrate; one or more power devices arranged on the power substrate; an assembly comprising a top surface, first sides, and second sides; power contacts; signal contacts; and signal interconnections configured to connect the signal contacts to respective connections on the one or more power devices to provide signals to the one or more power devices, wherein the signal contacts are configured on the top surface, in the top surface, and/or to extend from the top surface; wherein the signal contacts are arranged in a middle section of the top surface between the second sides; wherein the power package has an overall gate-loop inductance that is generated based on a construction and configuration of the signal contacts and/or the signal interconnections; and wherein the signal contacts and/or the signal interconnections are constructed and configured to have a similar overall gate-loop inductance, where a similar overall gate-loop inductance is within 3 nH. Specifically, the prior art of record fails to disclose wherein the power package has an overall gate-loop inductance that is generated based on a construction and configuration of the signal contacts and/or the signal interconnections; and wherein the signal contacts and/or the signal interconnections are constructed and configured to have a similar overall gate-loop inductance, where a similar overall gate-loop inductance is within 3 nH.
Regarding claim 71, the prior art of record fails to disclose a power package comprising: a power substrate; one or more power devices arranged on the power substrate; an assembly comprising a top surface, first sides, and second sides; power contacts; and signal contacts; and signal interconnections configured to connect the signal contacts to respective connections on the one or more power devices to provide signals to the one or more power devices, wherein the power package has an overall gate-loop inductance that is generated based on a construction and configuration of the signal contacts and/or the signal interconnections; and wherein the signal contacts and/or the signal interconnections are constructed and configured to have a similar overall gate-loop inductance, where a similar overall gate-loop inductance is within 0% - 6% in inductance. Specifically, the prior art does not disclose wherein the power package has an overall gate-loop inductance that is generated based on a construction and configuration of the signal contacts and/or the signal interconnections, and wherein the signal contacts and/or the signal interconnections are constructed and configured to have a similar overall gate-loop inductance, and where a similar overall gate-loop inductance is within 0% - 6% in inductance.
For this reason, claims 72-76 are also allowable as dependents of claim 71.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments, see pgs. 9-13, filed 6/26/2026, with respect to the rejection(s) of claim(s) 1-6, 10, 13-14, 22, 26, and 36-39 under 35 U.S.C. 102 and 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art. Specifically, Nikitin remedies the deficiencies of Hatano with respect to at least amended claim 1. See the rejection to claim 1 above.
With respect to Applicant’s arguments regarding Hatano, Applicant's arguments filed 6/26/2026 have been fully considered but they are not persuasive. Applicant argued that Hatano instead places terminals at or near the package boundary, and that the terminals are not centrally on/in the package. Applicant further argues that the mapping of Hatano to the claimed “middle section” improperly broadens Hatano’s disclosure and ignores the side-mounted placement of the GT1 and SST1 terminals shown in Hatano’s Fig. 64.
Examiner disagrees with Applicant’s arguments. Examiner asserts that the claim language “a middle section” in claim 1 is broad enough to reasonably be interpreted as any arbitrary region having symmetrical boundaries across the X axis and symmetrical boundaries across the Y axis (as shown in the figure attached to the rejection of claim 1), and there is no claim language particularly limiting the breadth of the region. Furthermore, Examiner asserts that there is not claim language particularly defining which portion of the contacts must be within a middle section. Hatano discloses a contact on the top surface of device, even if the contact comprises a portion bending toward the side surface of the device. In this way, Hatano also discloses a contact within a middle section of the device, even if the contact comprises a portion of the contact which is outside of a middle section of the device. For these reasons, Examiner does not find Applicant’s arguments to be persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.J.S./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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