Prosecution Insights
Last updated: August 17, 2026
Application No. 18/503,013

Semiconductor Device and Methods of Making and Using Pre-Molded Bridge Die

Final Rejection §102§103
Filed
Nov 06, 2023
Examiner
RAHMAN, MOIN M
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Stats Chippac Pte. Ltd.
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
648 granted / 745 resolved
+19.0% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
45 currently pending
Career history
804
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
56.4%
+16.4% vs TC avg
§102
26.9%
-13.1% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 745 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Arguments Applicant’s reply filed on 05/06/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL. Election/Restrictions Claims 1 and 5-6, previously withdrawn from consideration as a result of a previous restriction requirement, have been rejoined and are now allowed as being dependent upon allowable independent claim or as including the common allowable subject matter as the elected, claimed invention. Pursuant to the procedures set forth in MPEP § 821.04, the restriction requirement is hereby withdrawn as to any claim that requires all the limitations of an allowable claim. Because all claims previously withdrawn from consideration under 37 CFR 1.142 have been rejoined, the restriction requirement as set forth in the Office action mailed on 01/05/2026 is hereby withdrawn. In view of the withdrawal of the restriction requirement as to the rejoined inventions, applicant(s) are advised that if any claim presented in a continuation or divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215,170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 20, 22-24 and 26 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by YIM et al (US 2024/0395720 A1; hereafter YIM). PNG media_image1.png 483 764 media_image1.png Greyscale Regarding claim 20. YIM discloses a semiconductor device (Fig 1, Para [ 0036-0057]), comprising: a first interconnect structure (the first redistribution layer structure 110, Para [ 0037]) including a first insulating layer (first dielectric layer 111) and a first conductive layer (first redistribution layer lines 113, Para [ 0038]); a pre-molded bridge die (construed as pre- molded die [130, 160,172], Para [ 0036-0037, 0055]) disposed over the first interconnect structure(the first redistribution layer structure 110, Para [ 0037]), wherein the pre-molded bridge die (construed as pre-molded die [130, 160,172], Para [ 0036-0037]) includes, a bridge die (molded die [130], Para [ 0036-0037]), and a first encapsulant ( insulation layer 173 , Para [ 0057]) deposited over the bridge die (die [130], Para [ 0036-0037]); a second encapsulant (second silicon insulation layer 174, Para [ 0057]) deposited over the pre-molded bridge die (die [130], Para [ 0036-0037]), wherein the second encapsulant (second silicon insulation layer 174, Para [ 0057]) physically contacts the first encapsulant (insulation layer 173, Para [ 0057]); and a second interconnect structure (redistribution layer structure 190, Para [ 0058]) including a second insulating layer (second dielectric layer 191, Para [ 0069]) and a second conductive layer (redistribution layer lines 193,) disposed over the second encapsulant (second silicon insulation layer 174, Para [ 0057]) and pre-molded bridge die (construed as pre- molded die [130, 160,172], Para [ 0036-0037, 0055]) with the first encapsulant (insulation layer 173, Para [ 0057]) and second encapsulant (second silicon insulation layer 174, Para [ 0057]) both disposed between the first interconnect structure (the first redistribution layer structure 110, Para [ 0037]) and second interconnect structure (redistribution layer structure 190, Para [ 0058]). Regarding claim 22. YIM discloses the semiconductor device of claim 20, YIM further discloses wherein the pre-molded bridge die (construed as pre- molded die [130, 160,172], Para [ 0036-0037, 0055]) further includes a plurality of micropillars (bonding pads 171, Para [ 0044]) formed over the bridge die (die [130], Para [ 0036-0037]). Regarding claim 23. YIM discloses the semiconductor device of claim 20, wherein the pre-molded bridge die includes a protective layer (molding material 160, Para [ 0053]) formed over the bridge die (die [130], Para [ 0036-0037]) under the first encapsulant (insulation layer 173, Para [ 0057]). Regarding claim 24. YIM discloses the semiconductor device of claim 20, wherein a surface of the first encapsulant (insulation layer 173, Para [ 0057]) is coplanar to a surface of an interconnect structure (the first redistribution layer structure 110, Para [ 0037]) of the pre-molded bridge die (construed as pre- molded die [130, 160,172], Para [ 0036-0037, 0055]). Regarding claim 26. YIM discloses the semiconductor device of claim 20, wherein a surface of the first encapsulant (insulation layer 173, Para [ 0057]) is coplanar with a surface of the second encapsulant (second silicon insulation layer 174, Para [ 0057]). Claim Rejection- 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over YIM et al (US 2024/0395720 A1; hereafter YIM) in view of Lin et al (US 2015/0287708 A1; hereafter Lin). Regarding claim 25. YIM discloses the semiconductor device of claim 20, But YIM does not disclose explicitly further including a conductive pillar extending through the second encapsulant from the first interconnect structure to the second interconnect structure. In a similar field of endeavor, Lin discloses a conductive pillar (Fig, [32], bumps 776, Para [ 0076]) extending through the encapsulant (Fig, [32],insulating or passivation layer 764, Para [ 0236]) from the first interconnect structure (Fig, [32], elements [700], construed as first interconnect structure, Para [ 0217]) to the second interconnect structure (Fig, [32], elements [800], construed as second interconnect structure, Para [ 0255]). Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine YIM in light of LIN teaching “a conductive pillar (Fig, [32], bumps 776, Para [ 0076]) extending through the encapsulant (Fig, [32],insulating or passivation layer 764, Para [ 0236]) from the first interconnect structure (Fig, [32], elements [700], construed as first interconnect structure, Para [ 0217]) to the second interconnect structure (Fig, [32], elements [800], construed as second interconnect structure, Para [ 0255])” for further advantage such as reliable vertical electrical interconnect structure for the semiconductor devices. Allowable Subject Matter Claims 1, 5-6, 14, 18-19 and 27 are allowed. The following is the Examiner's Reasons for Allowance: The prior art fails to disclose and would not have rendered obvious: wherein the first encapsulant physically contacts the first conductive pillar, second conductive pillar, and die-attach film; depositing a second encapsulant over the pre-molded bridge die; disposing a second interconnect structure over the second encapsulant and pre-molded bridge die; disposing a first semiconductor die over the second interconnect structure within a footprint of the pre-molded bridge die; and disposing a second semiconductor die over the second interconnect structure within the footprint of the pre-molded bridge die, wherein the second semiconductor die is electrically connected to the first semiconductor die through the first conductive pillar, bridge die, and second conductive pillar., as recited in claim 1. Claims 5-6 are allowed based on the dependency of claim 1. wherein the first encapsulant physically contacts the first conductive pillar, second conductive pillar, and die-attach film; a second encapsulant deposited over the pre-molded bridge die; a second interconnect structure disposed over the second encapsulant and pre-molded bridge die; a first semiconductor die disposed over the second interconnect structure within a footprint of the pre-molded bridge die; and a second semiconductor die disposed over the second interconnect structure within the footprint of the pre-molded bridge die, wherein the second semiconductor die is electrically connected to the first semiconductor die through the first conductive pillar, bridge die, and second conductive pillar, as recited in claim 14. Claims 18-19 and 27 are allowed based on the dependency of claim 14. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOIN M RAHMAN/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Nov 06, 2023
Application Filed
Apr 21, 2026
Non-Final Rejection mailed — §102, §103
May 06, 2026
Response Filed
Jul 22, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+14.3%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 745 resolved cases by this examiner. Grant probability derived from career allowance rate.

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