Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Applicant's election of group I without traverse: claims 1-12, cancellation of claims 13-20 and submission of new claims 21-28, in the “Response to Election / Restriction Filed - 04/07/2026” is/are acknowledged. This office action considers claims 1-12, 21-28, in “Claims - 04/07/2026”, pending for prosecution.
Priority
Acknowledgment is made of applicant's claim for domestic benefit based on provisional application 63/507,205 filed on 06/09/2023.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-2, 4-5, 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Verma et al. (US 20220270973 A1 – hereinafter Verma).
Regarding Claim 1, Verma teaches a method (see the entire document; Figs. 1-2; specifically, ([0021] - [0022]), and as cited below), comprising:
forming a lower transistor (116 – Fig. 1 – [0021]) in a lower wafer (100), wherein the lower transistor (116) comprises a lower source/drain region (116D);
forming a contact plug (108a) electrically connecting to the lower source/drain region (116D);
forming a metal line (108b) over the lower transistor (116) and as a part of the lower wafer (100), wherein a first portion of the metal line is vertically aligned to the lower source/drain region (part of 108b that aligns with 108a);
bonding an upper wafer (200) to the lower wafer (100 – Fig. 2 shows wafers 100 and 200 are bonded);
forming an upper transistor (216 – [0022]) in the upper wafer (200), wherein the upper transistor comprises an upper source/drain region (216D), and the upper source/drain region (216D) is vertically aligned to a second portion of the metal line (right portion of 108b), and wherein the upper transistor and the lower transistor collectively form a CFET (as shown in Fig. 2);
forming a first interconnect structure (right 110b) on the lower wafer (100) and electrically connecting to the lower transistor (100); and
forming a second interconnect structure (210b) on the upper wafer (200) and electrically connecting to the upper transistor (216 – see Fig.2).
Regarding Claim 2, Verma teaches the method of claim 1 further comprising, after the upper transistor is formed, forming a deep contact plug penetrating through the lower source/drain region, wherein the deep contact plug contacts the metal line and electrically connects the lower source/drain region to the metal line (Fig 2 shows 208a connects to 216D which connects of 108b).
Regarding Claim 4, Verma teaches the method of claim 2, wherein the first interconnect structure is formed after the deep contact plug is formed ([0021]).
Regarding Claim 5, Verma teaches the method of claim 1 further comprising:
forming a via, wherein the metal line is connected to the contact plug (108a) through the via (Fig. 2 shows 108b is connected to 108a).
Regarding Claim 9, Verma teaches the method of claim 1 further comprising, after the upper transistor is formed, forming a deep contact plug penetrating through the upper source/drain region, wherein the deep contact plug contacts the metal line and electrically connects the upper source/drain region to the metal line (Fig. 1 shows 208a connecting to 216D).
Regarding Claim 10, Verma teaches the method of claim 1, wherein the upper wafer is bonded to the lower wafer through a face-to-back bonding process ([0023]).
Regarding Claim 11, Verma teaches the method of claim 1, wherein the upper wafer is bonded to the lower wafer through a back-to-back bonding process ([0033]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Verma in view of Smith et al. (US 20220122892 A1 - hereinafter Smith).
Regarding Claim 12, Verma teaches claim 1 from which claim 12 depends. But Verma does not expressly disclose wherein each of the lower transistor and the upper transistor comprises a transistor selected from a gate-all-around transistor and a fin field-effect transistor.
It is well known in the art to implement a lower transistor bonded to an upper transistor to form a CMOS/CFET in a FinFet or GAA-like process as is also taught by Smith (Smith – [0053] – “This can be achieved through the incorporation of multiple wafer bonding to carrier wafers and wafer flips to allow access to the CFET backside such that a FINFET or GAA-like process flow can be incorporated into a CFET device. As was stated earlier, typical thermal-aware FINFET or GAA flows have not been incorporated into CFET devices as the lower tier devices and transistors are generally not accessible as the upper tier devices and transistors are being created”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein each of the lower transistor and the upper transistor comprises a transistor selected from a gate-all-around transistor and a fin field-effect transistor as taught by Smith into Verma.
An ordinary artisan would have been motivated to integrate Smith structure into Verma structure in the manner set forth above for, at least, for obvious benefit of “high temperature processing can be maintained in an order consistent with FINFET and GAA processing” – Smith [0053].
Claims 21-25 is rejected under 35 U.S.C. 103 as being unpatentable over Verma in view of Chang et al. (US 20210375761 A1 - hereinafter Chang).
Regarding Claim 21, Verma teaches a method (see the entire document; Figs. 1-2; specifically, ([0021] - [0022]), and as cited below), comprising:
forming a lower transistor (116 – Fig. 1 – [0021]) comprising:
growing a lower source/drain region (116D);
forming a contact plug (108a) electrically connecting to the lower source/drain region (116D);
forming an upper transistor (216 – [0022]) overlapping the lower transistor (116 – as seen in Fig. 2), wherein the forming the upper transistor (216) comprises:
growing an upper source/drain region (216D) that is vertically offset from the lower source/drain region (that is, 116 and 216 are vertically offset as seen in Fig. 2), wherein the upper source/drain region (216D) is electrically connected to the lower source/drain region (116) through an electrical path (as seen in Fig. 2);
forming a first interconnect structure (110b) electrically connecting to the lower transistor (116); and
forming a second interconnect structure (210b) electrically connecting to the upper transistor (216), wherein the first interconnect structure (110b) and the second interconnect structure (210b) are on opposing sides of a combined structure comprising the lower transistor (116) and the upper transistor (216).
But Verma as applied above does not expressly disclose growing the lower and upper source/drain region via an epitaxial process.
However, it is widely known in the art to form source/drain region via an epitaxial process as is also taught by Chang (Chang – [0105]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the growing the lower and upper source/drain region via an epitaxial process as taught by Chang into Verma.
An ordinary artisan would have been motivated to integrate Chang structure into Verma structure in the manner set forth above for, at least, for obvious benefit of improved electrical performance and lower contact resistance as is well known.
Regarding claim 22, the combination of Verma and Chang teaches the method of claim 21, wherein the electrical path comprises a metal line between the lower transistor and the upper transistor (Fig. 2 of Verma – since 210b and 110b are connected).
Regarding claim 23, the combination of Verma and Chang teaches the method of claim 22, wherein the metal line comprises a first portion overlapping the lower source/drain region, and a second portion overlapped by the upper source/drain region (Fig. 2 of Verma).
Regarding claim 24, the combination of Verma and Chang teaches the method of claim 22 further comprising: forming a first deep contact plug penetrating through the lower source/drain region; and forming a second deep contact plug penetrating through the upper source/drain region, wherein the lower source/drain region is electrically connected to the upper source/drain region through the first deep contact plug, the metal line, and the second deep contact plug (Fig. 2 of Verma).
Regarding claim 25, the combination of Verma and Chang teaches the method of claim 24 further comprising: forming an etch stop layer underlying and contacting the metal line, wherein the first deep contact plug penetrates through the etch stop layer, and the metal line contacts the etch stop layer to form a horizontal interface (see for details of etch stop layer – Chang [0054]).
Claims 26-28 is rejected under 35 U.S.C. 103 as being unpatentable over Verma in view of Chang.
Regarding Claim 26, Verma teaches a method (see the entire document; Figs. 1-2; specifically, ([0021] - [0022]), and as cited below), comprising:
forming complementary field-effect transistors (transistors in Fig. 2) comprising:
forming a lower transistor (116 – Fig. 1 – [0021]) comprising growing a lower source/drain region (116D); and
forming an upper transistor (216 – [0022]) overlapping the lower transistor (116), wherein the forming the upper transistor (216) comprises growing an upper source/drain region (216D) that is vertically misaligned from the lower source/drain region (116D);
forming a horizontal metal line ({110b, 210b}) between the lower transistor (116) and the upper transistor (216), wherein the horizontal metal line connects the lower source/drain region (116D) to the upper source/drain region (216D);
forming a lower contact plug (108a) contacting a bottom surface of the horizontal metal line (as seen in Fig. 2), wherein the lower contact plug (108a) connects the horizontal metal line ({110b, 210b}) to the lower source/drain region (116D); and
forming an upper contact plug (208a) contacting a top surface of the horizontal metal line ({110b, 210b}), wherein the upper contact plug (208a) connects the horizontal metal line to the upper source/drain region (216D).
But Verma as applied above does not expressly disclose growing the lower and upper source/drain region via an epitaxial process.
However, it is widely known in the art to form source/drain region via an epitaxial process as is also taught by Chang (Chang – [0105]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the growing the lower and upper source/drain region via an epitaxial process as taught by Chang into Verma.
An ordinary artisan would have been motivated to integrate Chang structure into Verma structure in the manner set forth above for, at least, for obvious benefit of improved electrical performance and lower contact resistance as is well known.
Regarding claim 27, the combination of Verma and Chang teaches the method of claim 26, wherein the lower contact plug is formed as penetrating through the lower source/drain region, wherein the upper contact plug penetrates through the upper source/drain region (see Fig. 2).
Regarding claim 28, the combination of Verma and Chang teaches the method of claim 26 further comprising forming an etch stop layer contacting the horizontal metal line to form a horizontal interface, wherein the upper contact plug penetrates through the etch stop layer (see for details of etch stop layer – Chang [0054]).
Allowable Subject Matter
Claims 3, 6-8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 3: The method of claim 2, wherein the lower transistor comprises a semiconductor substrate, and the method further comprise: removing the semiconductor substrate to reveal the lower source/drain region, wherein the deep contact plug is formed after the semiconductor substrate is removed.
Regarding claim 6: The method of claim 1 further comprising: forming a etch stop layer over the lower transistor; forming a dielectric layer over and contacting the etch stop layer; etching the dielectric layer to form a first trench, wherein the etching is stopped on the etch stop layer, and a first side of the etch stop layer is exposed; and etching-through the etch stop layer from the first side, wherein the metal line is formed in the first trench.
Claim 7 depends from claim 6.
Regarding claim 8: The method of claim 1 further comprising: forming a first bond layer over the metal line and as a part of the lower wafer, wherein the upper wafer comprises a second bond layer bonding to the first bond layer; and removing an additional semiconductor substrate of the upper wafer to reveal a multi- layer stack, wherein the upper transistor is formed based on the multi-layer stack.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
Prosecution Insights