Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election without traverse of Species I in the reply filed on 2 Feb 2026 is acknowledged.
Claims 3-6 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2 Feb 2026.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application TW 112138094 filed on 10/04/2023. The foreign application is not in English. The certified copy of the foreign priority application TW112138094 has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application TW112138094that is not in English, an English translation of the non-English language foreign TW112138094 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Abstract
The abstract of the disclosure is objected to because it repeats itself. The second and third sentence both read, “The first memory cell includes a control terminal, a data terminal and a source terminal.”
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, and 7-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al (US Patent 10978122) hereinafter referred to as Tseng, and Oka et al. (US Pub 20190147931), hereinafter referred to as Oka.
Regarding claim 1, Tseng teaches a memory device comprising: a first memory cell (Tseng, 210, Fig. 5) comprising a control terminal (Tseng, Fig. 5, see diagram below), a first data terminal (Tseng, Fig. 5, see diagram below), and a source terminal (Tseng, Fig. 5, see diagram below); a second memory cell (Tseng, 220, Fig. 5) comprising a control terminal (Tseng, Fig. 5, see diagram below), a first data terminal (Tseng, Fig. 5, see diagram below)and a source terminal (Tseng, Fig. 5, see diagram below); and a bit line coupled to the first data terminal of the first memory cell and the first data terminal of the second memory cell (Tseng, BL1, Fig. 5).
Tseng does not teach a word line coupled to the control terminal of the first memory cell and the control terminal of the second memory cell; a first source line coupled to the source terminal of the first memory cell and configured to receive a first source voltage; a second source line coupled to the source terminal of the second memory cell and configured to receive a second source voltage, the second source voltage being different from the first source voltage.
However, Oka teaches a memory device with multiple cells, which shows; a word line coupled to the control terminal of the first memory cell and the control terminal of the second memory cell (Oka, WL0, Fig. 6); a first source line coupled to the source terminal of the first memory cell and configured to receive a first source voltage (Oka, SL0, Fig. 6); and a second source line coupled to the source terminal of the second memory cell and configured to receive a second source voltage (Oka, Fig. 6 SL1).
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Tseng additionally teaches teach wherein the cells can be selectively activated or deactivated by sending enabling or disabling voltages through the word lines using different voltages (Tseng, Col. 5, line 5-Col 6, line 28).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the memory device of Tseng with the word line, source line and vertical configuration of Oka, using the enabling and disabling voltage of Tseng, through the source lines of Oka to create an enabling and disabling system transmitted through the source lines. This would result in reduced circuit size, improved performance and reliability and would suppress layout size.
Regarding claim 2, modified Tseng teaches he memory device of Claim 1, wherein the first source voltage is one of an enabling voltage and a disabling voltage, and the second source voltage is a remaining one of the enabling voltage and the disabling voltage (Tseng, Col. 5, line 5-Col 6, line 28).
Regarding claim 7, modified Tseng teaches he memory device of Claim 1, wherein: the first memory cell further comprises a second data terminal (Tseng, Fig. 5, see diagram below);
the second memory cell further comprises a second data terminal (Tseng, Fig. 5, see diagram below);
and the memory device further comprises a second bit line coupled to the second data terminal of the first memory cell and the second data terminal of the second memory cell (Tseng, BL2, Fig. 5).
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Regarding claim 8, modified Tseng teaches the memory device of Claim 7, wherein: the first memory cell comprises: a first memory element (Tseng, 110, Fig. 5) comprising a first terminal coupled to the first data terminal of the first memory cell (Tseng, Fig. 5, see diagram below); and a second terminal (Tseng, Fig. 5, see diagram below); a second memory element (Tseng, 120, Fig. 5) comprising; a first terminal coupled to the second data terminal of the first memory cell (Tseng, Fig. 5, see diagram below), and a second terminal(Tseng, Fig. 5, see diagram below); a first transistor (Tseng, 1310, Fig. 5) comprising a control terminal coupled to the control terminal of the first memory cell, a first terminal coupled to the second terminal of the first memory element of the first memory cell, and a second terminal coupled to the source terminal of the first memory cell; a second transistor (Tseng, 1320, Fig. 5) comprising a control terminal coupled to the control terminal of the first memory cell, a first terminal coupled to the second terminal of the second memory element of the first memory cell, and a second terminal coupled to the source terminal of the first memory cell; and a third transistor (Tseng, 1330, Fig. 5) comprising a control terminal coupled to the control terminal of the first memory cell, a first terminal coupled to the first terminal of the first transistor of the first memory cell, and a second terminal coupled to the first terminal of the second transistor of the first memory cell; and the second memory cell comprises: a first memory element (Tseng, 130, Fig. 5) comprising a first terminal coupled to the first data terminal of the second memory cell, and a second terminal (Tseng, Fig. 5, see diagram below); a second memory element Tseng, 140, Fig. 5) comprising a first terminal coupled to the second data terminal of the second memory cell, and a second terminal (Tseng, Fig. 5, see diagram below); a first transistor (Tseng, 1340, Fig. 5) comprising a control terminal coupled to the control terminal of the second memory cell, a first terminal coupled to the second terminal of the first memory element of the second memory cell, and a second terminal coupled to the source terminal of the second memory cell; a second transistor (Tseng, 1350, Fig. 5) comprising a control terminal coupled to the control terminal of the second memory cell, a first terminal coupled to the second terminal of the second memory element of the second memory cell, and a second terminal coupled to the source terminal of the second memory cell; and a third transistor (Tseng, 1360, Fig. 5) comprising a control terminal coupled to the control terminal of the second memory cell, a first terminal coupled to the first terminal of the first transistor of the second memory cell, and a second terminal coupled to the first terminal of the second transistor of the second memory cell.
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Regarding claim 9, modified Tseng teaches the memory device of Claim 8, wherein the first memory element and the second memory element of the first memory cell and the first memory element and the second memory element of the second memory cell are magnetic tunnel junctions (Tseng, Col. 5, lines 43-47), and the first transistor, the second transistor and the third transistor of the first memory cell and the first transistor, the second transistor and the third transistor of the second memory cell are N-type transistors (Tseng, Col. 3, lines 25-35, Col 5, lines 29-31).
Regarding claim 10, Tseng teaches a memory device comprising: a first source line formed along a first direction (Tseng, Fig. 9, 930(SL9)); a first bit line formed along the first direction (Tseng, 950(BL 92), Fig. 9); a second bit line formed along the first direction (Tseng, 950(BL91), Fig. 9); a first memory cell (Tseng. 210, Fig. 6) comprising: a first diffusion layer (Tseng, 610, Fig. 6) at least partially overlapping with the first bit line (Tseng, Col 6, lines 13-21); and a third diffusion layer (Tseng, 610, Fig. 6) at least partially overlapping with the first bit line (Tseng, Col. 6, lines 13-21); a second memory cell (Tseng, 220, Fig. 6) comprising: a second diffusion layer (Tseng, 610, Fig. 6) at least partially overlapping with the second bit line (Tseng, Col. 6, lines 13-21); and a fourth diffusion layer at least partially overlapping with the second bit line (Tseng, Col. 6, lines 13-21); a first bit line connection layer (Tseng, 935, Fig. 9) formed along a second direction and at least partially overlapping with the first diffusion layer and the second diffusion layer; and a second bit line connection layer (Tseng, 935, Fig. 9) formed along a second direction and at least partially overlapping with the third diffusion layer and the fourth diffusion layer.
Tseng does not teach a second source line formed along the first direction, the second source line and the first source line being separated from each other.
However, Oka teaches a memory device with multiple cells, which shows, a first source line coupled to the source terminal of the first memory cell (Oka, SL0, Fig. 6); and a second source line coupled to the source terminal of the second memory cell (Oka, Fig. 6 SL1), wherein the first source line and the second source line are separated from each other.
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the memory device of Tseng with the second source line and vertical configuration of Oka to create a memory device with two cells and two source lines. This would result in reduced circuit size, improve reliability and would suppress layout area.
Regarding claim 11, modified Tseng teaches the memory device of Claim 10, wherein:
the first memory cell (Tseng, 210, Fig 6) further comprises: a first polysilicon layer (Tseng, WL1, Fig. 6, Col. 8, lines 24-34) formed along the second direction and at least partially overlapping with the first source line and the first bit line; a third polysilicon layer ((Tseng, WL2, Fig. 6, Col. 8, lines 24-34) formed along the second direction and at least partially overlapping with the first source line and the first bit line, wherein the first diffusion layer is located between the first polysilicon layer and the third polysilicon layer(Tseng, 610, Fig. 6); a fifth polysilicon layer (Tseng, WL3, Fig. 6, Col. 8, lines 24-34) formed along the second direction and at least partially overlapping with the first source line and the first bit line, wherein the third diffusion layer is located between the third polysilicon layer and the fifth polysilicon layer (Tseng, 610, Fig. 6); a first magnetic tunnel junction overlapping with the first diffusion layer and the first bit line (Tseng, 110, Fig 6, Col. 2, lines 32-51, Col 5, lines 43-47) ; a third magnetic tunnel junction overlapping with the third diffusion layer and the first bit line (Tseng, 120, Fig 6, Col. 2, lines 32-51, Col 5, lines 43-47); a fifth diffusion layer at least partially overlapping with the first source line (Tseng, 610, Fig. 6); and a sixth diffusion layer at least partially overlapping with the first source line(Tseng, 610, Fig. 6,): and the second memory cell (Tseng, 220, Fig. 6) further comprises; a second polysilicon layer (Tseng, WL4, Fig. 6, Col. 8, lines 24-34) formed along the second direction and at least partially overlapping with the second source line and the second bit line; a fourth polysilicon layer (Tseng, WL5, Fig. 6, Col. 8, lines 24-34) formed along the second direction and at least partially overlapping with the second source line and the second bit line, wherein the second diffusion layer is located between the second polysilicon layer and the fourth polysilicon layer (Tseng, 610, 610); a sixth polysilicon layer formed along the second direction and at least partially overlapping with the second source line and the second bit line (Tseng, WL6, Fig. 6, Col. 8, lines 24-34), wherein the fourth diffusion layer is located between the fourth polysilicon layer and the sixth polysilicon layer (Tseng, 610, Fig. 6); a second magnetic tunnel junction overlapping with the second diffusion layer and the second bit line (Tseng, 130, Fig 6, Col. 2, lines 32-51, Col 5, lines 43-47); a fourth magnetic tunnel junction overlapping with the fourth diffusion layer and the second bit line (Tseng, 140, Fig 6, Col. 2, lines 32-51, Col 5, lines 43-47); a seventh diffusion layer at least partially overlapping with the second source line (Tseng, 610, Fig. 6); and an eighth diffusion layer at least partially overlapping with the second source line (Tseng, 610, Fig. 6).
Regarding claim 12, modified Tseng teaches he memory device of Claim 11, wherein:
the first source line and the second source line are formed by a same conductive layer (Ok, para. 75); the first bit line and the second bit line are formed by a same conductive layer (Tseng, Fig. 9, 950(BL91), 950(BL92), Col. 8, lines 24-34); the first bit line connection layer and the second bit line connection layer are formed by a same conductive layer (Tseng, 935, Col. 8, lines 43-50);
the first polysilicon layer, the second polysilicon layer, the third polysilicon layer, the fourth polysilicon layer, the fifth polysilicon layer and the sixth polysilicon layer are formed by a same polysilicon layer (Tseng, 920, Fig. 9, Col. 8, lines 11-20), and the first diffusion layer, the second diffusion layer, the third diffusion layer, the fourth diffusion layer, the fifth diffusion layer, the sixth diffusion layer, the seventh diffusion layer and the eighth diffusion layer are formed by a same diffusion layer (Tseng, 910, Fig. 9, and 610, Fig. 6).
Regarding claim 13, modified Tseng teaches the memory device of Claim 11, wherein the first polysilicon layer, the second polysilicon layer, the third polysilicon layer, the fourth polysilicon layer, the fifth polysilicon layer and the sixth polysilicon layer are separated from each other (Tseng, 920, Fig 9, and WL1-9, Fig. 6, Col. 8, lines 24-34).
Regarding claim 14, modified Tseng teaches the memory device of Claim 11, further comprising: a first contact overlapping with the fifth diffusion layer (Tseng, CT, Fig. 6 see diagram below); a second contact overlapping with the sixth diffusion layer (Tseng, CT, Fig. 6, see diagram below); a third contact overlapping with the seventh diffusion layer (Tseng, CT, Fig. 6, see diagram below, using the vertical configuration imported from Oka, the second and third contact would be separate contacts); and a fourth contact overlapping with the eighth diffusion layer (Tseng, CT, Fig. 6 see diagram below).
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Regarding claim 15, modified Tseng teaches the memory device of Claim 11, wherein:
the first memory cell further comprises a first via (Tseng, 971, Fig. 9) overlapping with the third diffusion layer and the third magnetic tunnel junction (Tseng, 9410, Fig. 9); and the second memory cell further comprises a second via (Tseng, 972, Fig. 9) overlapping with the second diffusion layer and the second magnetic tunnel junction (Tseng, 9420, Fig. 9).
Regarding, claim 16, modified Tseng teaches the memory device of Claim 10, wherein the first bit line and the second bit line are separated from each other, (Tseng, 950(BL91) and 950(BL92), Fig. 9)
Regarding claim 17, modified Tseng teaches the memory device of Claim 10, wherein the first direction is perpendicular to the second direction (Tseng, SL, WL, Fig. 6, SL is in first direction and WL is in second direction), (Oka, Fig. 7, para. 68, Second direction is orthogonal to the first direction).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Naik et al. (US Pub 20160225426) teaches a 3T2M memory cell array with two source lines and with two word lines in a horizontal configuration.
Lai et al. (US Pub 20170206970) teaches a memory array with 3T2M architecture and multiple source lines.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893