DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1, claims 1-8, in the reply filed on March 18, 2026 is acknowledged. Claims 9 and 10 have been cancelled by the Applicant. Action on the merits is as follows:
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the surface of the conductive circuit" in lines 10-11. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner has taken this to be “a surface of the conductive circuit”. Appropriate correction is required. Claim 6 inherits these deficiencies due to its dependency.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (Yu) (CN 219759581 U).
In regards to claim 1, Yu (Figs. 1, 3 and associated text and items) discloses a chip package with a metal shielding layer (Fig. 3, item 1)) comprising: a chip (item 10) which includes a first surface (item 11), a second surface (item 12) opposite to the first surface (item 11), and at least one die pad (item 13) and at least one chip protective layer (item 14) both arranged at the first surface (item 11); wherein the chip (item 10) is formed by cutting a wafer (item 2, Fig. 1); a redistribution layer (RDL) (item 20) which is disposed on a surface (item 141) of the chip protective layer (item 14) of the chip (item 10) and provided with at least one conductive circuit (item 21) for electrical connection with the die pad of the chip (item 10); the conductive circuit (item 21) is provided with at least one pad (item 22) which is exposed on a surface of the RDL (item 20) for being electrically connected with the outside; and a metal shielding layer (item 30) which is covering the second surface (item 12) of the chip for protecting the chip (item 10) and the conductive circuit (item 21) from external electromagnetic interference or light interference and improving structural strength of the chip package (Fig. 3, item 1).
The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, the limitation, “formed by cutting a wafer” has not been given patentable weight.
In regards to claim 2, Yu (Figs. 1, 3 and associated text and items) discloses wherein the metal shielding layer (item 30) is further made of silver (Ag) adhesive.
In regards to claim 3, Yu (Figs. 1, 3 and associated text and items) discloses wherein the metal shielding layer (item 30) further includes a surface (item 31) and a back surface (item 32) opposite to the surface (item 31) of the metal shielding layer (item 30); the chip (item 10) is disposed on the surface (item 31) of the metal shielding layer (item 30) while the back surface (item 32) of the metal shielding layer (item 30) is provided with a bottom protective layer (item 40).
In regards to claim 4, Yu (Figs. 1, 3 and associated text and items) discloses wherein the bottom protective layer (item 40) is further made of metal material selected from the group consisting of nickel (Ni) and gold (Au).
In regards to claim 5, Yu (Figs. 1, 3 and associated text and items) discloses wherein the RDL (item 20) further includes at least one first dielectric layer (item 24), at least one second dielectric layer (item 25), and at least one insulating layer (item 26); wherein the first dielectric layer (item 24) is covering the surface (item 141) of the chip protective layer (item 14) of the chip (item 10) and at least one first groove (item 241) is formed on the first dielectric layer (item 24) for allowing the die pad (item 13) to be exposed through the first groove (item 241); wherein the second dielectric layer (item 25) is covering a surface of the first dielectric layer (item 24) and provided with at least one second groove (item 251) which is communicating with the first groove (item 241) of the first dielectric layer (item 24); wherein the conductive circuit (item 21) is formed by a metal paste (item 21a) being filled into the first groove (item 241) and the second groove (item 251) fully and smoothly so that the die pad (item 13) is electrically connected with the conductive circuit (item 21); wherein the insulating layer (item 26) is arranged at a surface (item 252) of the second dielectric layer (item 25) and [the] a surface (item 23) of the conductive circuit (item 21) and provided with at least one opening (item 261) for allowing the pad (item 22) of the conductive circuit (item 21) to be exposed.
The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, the limitation, “formed by a metal paste being filled into the first groove” has not been given patentable weight.
In regards to claim 6, Yu (Figs. 1, 3 and associated text and items) discloses wherein the opening (item 261) of the insulating layer (item 26) is further provided with at least one solder ball (item 50) so that the pad (item 22) of the conductive circuit (item 21) is electrically connected with the outside by the solder ball (item 50).
In regards to claim 7, Yu (Figs. 1, 3 and associated text and items) discloses wherein the conductive circuit (item 21) is further made of silver (Ag) adhesive.
In regards to claim 8, Yu (Figs. 1, 3 and associated text and items) discloses wherein the conductive circuit (item 21) is further provided with a bump (item 27) which is made of metal material selected from the group consisting of nickel (Ni) and gold (Au).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 April 8, 2026
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