Attorney’s Docket Number: SD-230626-SKC
Filing Date: 11/08/2023
Claimed Priority Date: 03/17/2023 (KR10-2023-0035150)
Applicants: Choi et. al
Examiner: Aneesa Baig
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 11-13, 15-18 are rejected under 35 U.S.C. 102 (a)(1) as anticipated by Sim et al et al (US 20220158039 A1, Hereinafter Sim).
Regarding Claim 1, Sim shows (e.g., Fig 19a 19b, [0177]-[0189][0075]-[0078]) shows all aspects of the instant invention, including, A light emitting element, comprising:
a light emitting stack pattern (10) including:
a first semiconductor layer (11);
an active layer (12); and
a second semiconductor layer (13); and
an insulating film surrounding an outer circumferential surface of the light emitting stack pattern, wherein the insulating film includes:
a first layer (protective film 16);
a second layer surrounding the first layer (insulating film 14); and
a third layer surrounding the second layer (additional protective film 17), and the first layer and the third layer include a same material ([0184] additional protective film 17 may be the same silicon oxide (SiO.sub.x) thin film layer as the protective film 16).
Regarding Claim 2, Sim (e.g., Fig 19a 19b, [0177]-[0189][0075]-[0078]) shows the first and third layer may be silicon oxide
Regarding Claim 3, Sim shows the first (16) and third layer (17)may be hafnium oxide ([0140][0171]).
Regarding Claim 5, Sim (e.g., Fig 19a 19b, [0177]-[0189][0075]-[0078]) shows the second layer may be made of a material different than the first and third layers (e.g., insulating film 14 may be made of specifically ZnO, while 16 and 17 may be made of other materials).
Regarding Claim 6, Sim (Fig 19A) shows the first layer ( 16) disposed directly on the outer circumference surfaces of the inner layers.
Regarding Claim 7, Sim ([0009]) shows first semiconductor layer may include an n-type semiconductor layer doped with an n-type dopant, and the second semiconductor layer may include a p-type semiconductor layer doped with a p-type dopant.
Regarding Claim 8, Sim (e.g., Fig 19a 19b, [0177]-[0189][0075]-[0078]) shows an electrode layer (additional electrode 15) disposed on the semiconductor layers, and shows the stack of insulating films (16,14,17) surrounding a circumference of the LE stack pattern (10).
Regarding Claim 11, Sim (e.g., Fig 19a 19b, [0177]-[0189][0075]-[0078]) shows all aspects of the invention, including a light emitting element, comprising:
a light emitting stack pattern including a first semiconductor layer, an active layer, a second semiconductor layer, and an electrode layer, which are stacked on each other in a direction (11,12,13); and
an insulating film surrounding an outer circumferential surface of the light emitting stack pattern (10), wherein the insulating film includes:
a first layer disposed directly on the outer circumferential surface of the light emitting stack pattern to surround the light emitting stack pattern (16);
a second layer surrounding the first layer (14);
a third layer surrounding the second layer (17);
a fourth layer surrounding the third layer ; and
a fifth layer surrounding the fourth layer (the second and third insulating layer may be provided in the form of a multi-layer, where the second film (14) and third film (17) may include at least two layers and that the third film may include a inorganic insulating material ([0078][140]-[141][0173]-[0184]), and
the first layer and the third layer include a same material , and
the second layer includes a material different from a material of the first and third layers (([0184] additional protective film 17 may be the same silicon oxide (SiO.sub.x) thin film layer as the protective film 16, while 14 is ZnO).
Regarding Claim 12, See comments in Par 5 from claim 2, as they would be considered repeated here.
Regarding Claim 13, See comments in Par 6 from claim 3, as they would be considered repeated here.
Regarding Claim 15, Sim (e.g., Fig 19a 19b, [0177]-[0189][0075]-[0078]) shows the fourth and fifth layer may include an inorganic material ([0184]).
Regarding Claim 16, Sim (e.g., Fig 19a 19b, [0177]-[0189][0075]-[0078] Fig 21-25 [0215]-[0300]) shows display device comprising:
a substrate (SUB);
a first electrode and a second electrode that are disposed on the substrate and spaced apart from each other (CNE1 and CNE2); and
a light emitting element (LD) located on the substrate, the light emitting element including:
a first end portion electrically connected to the first electrode; and
a second end portion electrically connected to the second electrode (Fig 24 25 Show EP1 and EP2),
the light emitting element including:
a light emitting stack pattern (10) including:
a first semiconductor layer located at the second end portion (11);
an active layer disposed on the first semiconductor layer (12);
a second semiconductor layer disposed on the active layer (13); and
an electrode layer which is disposed on the second semiconductor layer and is located at the first end portion (15); and
an insulating film surrounding an outer circumferential surface of the light emitting stack pattern, wherein the insulating film includes:
a first layer disposed directly on the outer circumferential surface of the light emitting stack pattern (16);
a second layer surrounding the first layer (14); and
a third layer surrounding the second layer (17), and
the first layer and the third layer include a same material (See claims 11), and
the second layer includes a material different from a material of the first and third layers (See Claims 11)
Regarding Claim 17, See comments in Par 5 from claim 2, as they would be considered repeated here.
Regarding Claim 18, See comments in Par 6 from claim 3, as they would be considered repeated here.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4, 9, 10, 14, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sim in view of Cho et al (KR 20220033538 A-PDF provided, Hereinafter Cho).
Regarding Claim 4, while Sim ([0123] [0139]) shows the thicknesses of the first and third layer may be between a few nm to about a few tens of nm and that the thickness of third layer may be, it is silent about the specific thickness of 5nm or less for the first layer, and 10nm or less for the third layer.
However, ranges of thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. Sim shows that to achieve a desired thickness, a spin coating process may be performed repeatedly ([0119]).
Further, the range of thickness of 10nm or less is known. Cho, on the other hand and in a related field of LED devices, teaches the thickness of the insulating in a similar device may be in a range from about 5nm to 100nm, but it is not limited thereto, and that the thickness of the second insulating layer may be greater than the first insulating. Layer ([0160][0164]-[0175], Fig 4,5 and 21 [238]-[242]) and adjusting the thickness and the materials of the insulating layers may change the positive and negative fixed charges.
Accordingly, the specific range of thickness of the first layer and the third layer, absent any criticality, is only considered to be the “optimum” range of the thickness of the insulation structure disclosed by Sim that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired fixed charges, etch selectivity, manufacturing costs, etc. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as desired thickness of insulation material are used as design to result in certain fixed charges, as already suggested by Cho.
Since the applicant has not established the criticality (see next paragraph below) of the claimed thickness range, it would have been obvious to one of ordinary skill in the art to use these values in the structure of Sim.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 9, while the images of Sim do not explicitly show the fourth and fifth insulating layer, Sim does show in the paragraphs listed, the second and third insulating layer may be provided in the form of a multi-layer, where the second film (14) and third film (17) may include at least two layers and that the third film may include a inorganic insulating material ([0078][140]-[141][0173]-[0184]).
Further, see comments in paragraphs 19-25 of Claim 4 regarding thickness, as they would be considered repeated here.
Regarding Claim 10, see comments in paragraphs 26 of Claim 9, as they would be considered repeated here.
Regarding Claim 14, see comments in paragraphs 19-25 of Claim 4, as they would be considered repeated here
Regarding Claim 19, see comments in paragraphs 19-25 of Claim 4, as they would be considered repeated here
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sim in view of Youn et al (US 20190189969 A1, Hereinafter Youn) further in view of Kim et al (US 20220254830 A1, Hereinafter Kim)
Regarding Claim 20, Sim (e.g., Fig 19a 19b, [0177]-[0189][0075]-[0078] Fig 21-25 [0215]-[0300]) further shows
an emission area in which light is emitted from the light emitting element (EMA);
a non-emission area surrounding the emission area (Peripheral area [0255]);
a first alignment electrode disposed between the substrate and the first electrode; the first alignment electrode being electrically connected to the first electrode (EL1 [0236]);
a second alignment electrode disposed between the substrate and the second electrode; the second alignment electrode being electrically connected to the second electrode (EL2 [0236]);
a first bank located in the non-emission area, the first bank including an opening corresponding to the emission area (bank BNK may be a pixel defining layer[0257]);
While Sim shows the LD element may emit certain colored light, it is silent about including a color conversion layer and a color filter layer above the light emitting element.
Youn (Fig 6 [0107]-[0130]), on the other hand and in a related field of light emitting devices, teaches a color conversion layer (810,820) and filter (910,920) above the color conversion layer.
Youn includes both color conversion materials to enhance the luminous efficiency of red (R) light in the pixel corresponding to the first light emitting area E1 and luminous efficiency of green (G) light may be enhanced in the pixel corresponding to the second light emitting area E2 by the color conversion materials 810 and 820, and also, color purity of red (R) light, green (G) light, and blue (B) light may be enhanced by the color filters 910, 920, and 930.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have both color conversion layers and filters on top of the light emission areas in the device of Sim as taught by Youn, to enhance the luminous efficiency of each LE device.
While Sim shows pixel defining areas and has a bank of the sides of the emission areas, it does not show a second bank on top of a first bank.
Kim (Fig 8, [0117][0148]-[0150]), on the other hand and in a related field of LED devices, teaches bank patterns (BNK, Fig 8) placed on top of first bank patterns (BNP1, BNP2). Kim teaches these banks to further define the light emitting area based on the required design of the device.
Accordingly, it would have been obvious to include additional bank patterns in the structure of Sim, as taught by Kim to further shape the light emitting pattern of this device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose LED devices with multiple insulating layers.
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/ANEESA RIAZ BAIG/
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814