DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 11/08/23 & 12/04/23 & 10/08/24 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Yamada (US 2016/0027716) with intrinsic evidences from Tsurumi et al. (US 6,037,657), Hayasaka et al. (US 6,809,421) and Ohuchi et al. (US 6,197,617).
a. Re claim 1, Yamada discloses a semiconductor device (structure on fig. 1 excluding the cooler 6; see fig. 1 and related text; see remaining of disclosure for more details) to be arranged adjacent to a cooler 6 in a predetermined direction (vertical direction), the semiconductor device comprising: a semiconductor element 1 having main electrodes on opposite faces opposite in the predetermined direction (the main electrodes on top and bottom surfaces are not explicitly shown and disclosed but inherently exist because device 1 is disclosed in at least [0027]-[0033] to be electrically connected to layer 5b and layer 2b, and this connection configuration requires top and bottom electrodes for the types of devices such as IGBT and the likes that device 1 is disclosed to be in [0026]; in the alternative, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided device 1 with top and bottom electrodes to electrically connect to layers 5b and 2b as intended, and this as a non-inventive step of providing such a device with essential working parts as conventionally known in the art; see MPEP 2144.I&II); a substrate 5 (or 5&2) having an insulating base member 5a containing resin (glass epoxy resin; see [0027]), a front-face metal body 5b ([0027]) disposed on a front face of the insulating base member and a back-face metal body 5a disposed on a back face of the insulating base member, the front-face metal body being electrically connected to at least one of the main electrodes of the semiconductor element (explicit as per the above explanations); and a sealing body 8 (epoxy resin; [0033]) containing resin and sealing at least a part of the substrate and the semiconductor element, wherein a glass transition point of the insulating base member is referred to as Tgi (Tgi would be 120°C for epoxy glass as per col. 7 ln. 48-50 of Ohuchi et al. ‘617), a linear expansion coefficient of the insulating base member is referred to as αi (αi would be 15 ppm/°C for epoxy as per fig. 35 of Hayasaka et al. ‘421, noting that epoxy stands for epoxy resin as commonly done in the art), a glass transition point of the sealing body is referred to as Tgs (Tgs would be 150°C for epoxy resin as per col. 7 ln. 51-67 of Ohuchi et al. ‘617), and a linear expansion coefficient of the sealing body is referred to as αs (αs would be 14 ppm/°C for epoxy as per fig. 7 of Tsurumi et al. ‘657), and wherein the insulating base member and the sealing body satisfy a relationship of Tgs≥Tgi and a relationship of αi≥αs (explicit as per the above).
b. Re claim 2, the semiconductor element has, as the main electrodes, a first main (top) electrode and a second main (bottom) electrode disposed on the opposite faces in the predetermined direction, wherein the substrate (when it is 5&2) includes a first substrate 5 to which the first main electrode is connected and a second substrate 2 to which the second main electrode is connected, and wherein the first substrate and the second substrate are disposed to interpose the semiconductor element therebetween in the predetermined direction (explicit on fig. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada (US 2016/0027716) in view of Blaszczak et al. (US 2005/0067721, cited on IDS), with intrinsic evidences from Tsurumi et al. (US 6,037,657) and Hayasaka et al. (US 6,809,421).
a. Re claim 1, Yamada discloses a semiconductor device (structure on fig. 1 excluding the cooler 6; see fig. 1 and related text; see remaining of disclosure for more details) to be arranged adjacent to a cooler 6 in a predetermined direction (vertical direction), the semiconductor device comprising: a semiconductor element 1 having main electrodes on opposite faces opposite in the predetermined direction (the main electrodes on top and bottom surfaces are not explicitly shown and disclosed but inherently exist because device 1 is disclosed in at least [0027]-[0033] to be electrically connected to layer 5b and layer 2b, and this connection configuration requires top and bottom electrodes for the types of devices such as IGBT and the likes that device 1 is disclosed to be in [0026]; in the alternative, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided device 1 with top and bottom electrodes to electrically connect to layers 5b and 2b as intended, and this as a non-inventive step of providing such a device with essential working parts as conventionally known in the art; see MPEP 2144.I&II); a substrate 5 (or 5&2) having an insulating base member 5a containing resin (glass epoxy resin; see [0027]), a front-face metal body 5b ([0027]) disposed on a front face of the insulating base member and a back-face metal body 5a disposed on a back face of the insulating base member, the front-face metal body being electrically connected to at least one of the main electrodes of the semiconductor element (explicit as per the above explanations); and a sealing body 8 (epoxy resin; [0033]) containing resin and sealing at least a part of the substrate and the semiconductor element, wherein a glass transition point of the insulating base member is referred to as Tgi (Tgi of epoxy glass), a linear expansion coefficient of the insulating base member is referred to as αi (αi would be 15 ppm/°C for epoxy as per fig. 35 of Hayasaka et al. ‘421, noting that epoxy stands for epoxy resin as commonly done in the art), a glass transition point of the sealing body is referred to as Tgs (Tgs of epoxy resin), and a linear expansion coefficient of the sealing body is referred to as αs (αs would be 14 ppm/°C for epoxy as per fig. 7 of Tsurumi et al. ‘657), and wherein the insulating base member and the sealing body satisfy a relationship of αi≥αs (explicit as per the above). But Yamada does not explicitly disclose that the insulating base member and the sealing body satisfy a relationship of Tgs≥Tgi.
However, Blaszczak et al. disclose that having the glass transition point a sealing material 6 higher than the glass transition temperature (or point) of an epoxy glass substrate 3 allows the sealing material to control the final shape of a package device including a flat surfaces upon cooling (see figs 1-9 and at least [0014], [0068], [0072], [0080] and [0091]).
As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the sealing resin 8 to have a higher glass transition temperature (or point) than the one of the insulating substrate 5a (including also for the second insulating substrate 2a as necessary by making it of an epoxy glass too) in order to allow the sealing resin 8 to control the final shape of a package device including a flat surfaces upon cooling from soldering the cooler 6 to layer 2c. The modification would have resulted in having the insulating base member and the sealing body satisfying a relationship of Tgs≥Tgi.
b. Re claim 2, the semiconductor element has, as the main electrodes, a first main (top) electrode and a second main (bottom) electrode disposed on the opposite faces in the predetermined direction, wherein the substrate (when it is 5&2) includes a first substrate 5 to which the first main electrode is connected and a second substrate 2 to which the second main electrode is connected, and wherein the first substrate and the second substrate are disposed to interpose the semiconductor element therebetween in the predetermined direction (explicit on fig. 1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ogawa (US 2022/0051961) and Sono et al. (US 5,920,117) disclose structures similar to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
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/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899