DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 30 recites the limitation "conductive component" in lines 5-6. There is insufficient antecedent basis for this limitation in the claim, as this claim does not recite the use of a “conductive component”. Therefore, this claim is indefinite.
Claim Objections
Claims 22-29, 31-34, and 36-40 are objected to because of the following informalities: All of these claims are dependent upon cancelled claims. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No.11,929,328 in view of Lu et al, US Patent Application Publication 2012/0289015
Regarding claim 21, USP11929328 teaches a semiconductor device, comprising:
a layer of a source/drain component (claim 11);
a conductive component disposed over the layer (as recited in column 13, line 50);
a first barrier layer disposed directly on a side surface of the conductive component (column 13, lines 51-52); and
a second barrier layer disposed directly on a first portion, but not all, of a side surface of the first barrier layer (column 13, lines 53-57).
USP11929328 fails to recite the source/drain component is an epi-layer.
However, it is generally-known in the art that the source/drain component may be formed of epitaxial material. This is taught in figure 3 and [0027] of Lu with source/drain regions 31/32.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lu with that of USP11929328 because it is generally-known in the art that the source/drain component may be formed of epitaxial material, which increases the mobility in a pMOS transistor and nMOS transistor formed on the same semiconductor substrate, thereby improving the electrical functionality of semiconductor device.
Regarding claim 22, USP11929328 recites the first barrier layer and the second barrier layer have different material compositions (claim 3).
Regarding claim 23, USP11919328 recites interlayer dielectric (ILD) structure (dielectric layer) that is disposed over the epi-layer, wherein the ILD structure is in direct contact with a side surface of the second barrier layer and with a second portion of the side surface of the first barrier layer (column 13, lines 58-61).
Regarding claims 24-25, USP11919328 recites the ILD structure is in direct contact with an entirety of the side surface of the second barrier layer wherein a third portion of the side surface of the first barrier layer is in direct contact with the epi-layer (column 13, lines 58-61).
Regarding claim 26, USP11919328 recites the ILD structure includes a first ILD layer and a second ILD layer disposed over the first ILD layer; the first ILD layer is in direct contact with both the first barrier layer and the second barrier layer; and the second ILD layer is in direct contact with the second barrier layer but not with the first barrier layer (claim 18).
Regarding claim 27, USP11919328 recites the first barrier layer has a greater vertical dimension than the second barrier layer (column 13, line 51-57, wherein the second barrier layer doesn’t extend down the first barrier layer, which then makes the first barrier layer having a greater vertical dimension than the second barrier layer).
Regarding claim 28, USP11919328 recites a silicide layer disposed between the epi-layer and the conductive component, wherein the silicide layer is in direct contact with the first barrier layer, but not with the second barrier layer (claim 8).
Regarding claim 29, USP11919328 recites the first barrier layer has a first horizontally-extending segment; the second barrier layer has a second horizontally-extending segment; the first horizontally-segment of the first barrier layer is located over the second horizontally- extending segment of the second barrier layer; and the conductive component and the first horizontally-extending segment have substantially co- planar upper surfaces (column 13, lines 53-57).
Claims 30-34 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No.11,929,328 in view of Alptekin et al, US Patent 8,415,250
Regarding claim 30, USP11919328 recites a semiconductor device, comprising:
an layer of a source/drain component (column 14, lines 39);
a source/drain contact located over the layer, (column 14, lines 44-47); and
a plurality of at least four barrier layers located laterally adjacent to the conductive component, wherein a depth of a bottom surface of each of the barrier layers is correlated with a lateral proximity of the respective barrier layer to the source/drain contact (claims 13-16).
USP11919328 fails to teach the layer is an epi (epitaxial) layer and a bottom portion of the source/drain contact protrudes into the layer
However, it is generally-known in the art that this layer may be formed of epitaxial material. This is taught in column 6, lines 30-31 of Alptekin, Further, Alptekin teaches a bottom portion of the source/drain contact 162 protrudes into the layer 108 (figure 1P) as a means of providing a silicide contact and shape that provides lower contact resistance to improve the semiconductor device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Alptekin with that of USP11929328 because it is generally-known in the art that the source/drain component may be formed of epitaxial material, which increases the mobility in a pMOS transistor and nMOS transistor formed on the same semiconductor substrate, thereby improving the electrical functionality of semiconductor device and as a means of providing a silicide contact and shape that provides lower contact resistance to improve the semiconductor device.
Regarding claim 31, USP11929328 recites the plurality of at least four barrier layers include at least a first barrier layer located closest to the source/drain contact, a second barrier layer located farther from the source/drain contact than the first barrier layer, a third barrier layer located farther from the source/drain contact than the second barrier layer, and a fourth barrier layer located farther from the source/drain contact than the third barrier layer; a bottom surface of the first barrier layer has a first depth; a bottom surface of the second barrier layer has a second depth less than the first depth; a bottom surface of the third barrier layer has a third depth less than the second depth; and a bottom surface of the fourth barrier layer has a fourth depth less than the third depth (claims 13-16)
Regarding claim 32, USP11929328 recites the first barrier layer has a first material composition; the second barrier layer has a second material composition different from the first material composition; the third barrier layer has a third material composition different from the first material composition and the second material composition; and the fourth barrier layer has a fourth material composition different from the first material composition, the second material composition, and the third material composition (claim 20. Further, it would then be obvious that any additional barrier layer over the third layer may also have a different material component)
Regarding claim 33, USP11929328 recites a silicide layer disposed between the source/drain contact and the epi-layer; a first interlayer dielectric (ILD) layer disposed over the epi-layer; and a second ILD layer disposed over the first ILD layer; wherein: the bottom surface of the first barrier layer is in direct contact with the silicide layer; the bottom surface of the second barrier layer is in direct contact with the epi-layer but not with the silicide layer; the bottom surface of the third barrier layer is in direct contact with the first ILD layer but not with the second ILD layer; and the bottom surface of the fourth barrier layer is in direct contact with the second ILD layer (Claim 19).
Regarding claim 34, USP11929328 recites an upper surface of the first barrier layer is located over an upper surface of the second barrier layer; the upper surface of the second barrier layer is located over an upper surface of the third barrier layer; and the upper surface of the third barrier layer is located over an upper surface of the fourth barrier layer (claims 18-19).
Allowable Subject Matter
Claim 35 is allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 35, the prior art fails to anticipate or render obvious the claimed invention including “...etching the opening further into the ILD structure, wherein a portion of the first barrier layer remains on a portion of a sidewall of the ILD structure after the opening has been etched further into the ILD structure; depositing a second barrier layer in the opening, wherein a portion of the second barrier layer is formed on a sidewall of the portion of the first barrier layer; etching the opening at least partially into the epitaxial layer of the source/drain component, wherein the portion of the second barrier layer remains after the opening has been etched at least partially into the epitaxial layer of the source/drain component; depositing a third barrier layer in the opening, wherein a portion of the third barrier layer is formed on a sidewall of the portion of the second barrier layer; and forming a conductive contact in the opening, wherein a sidewall of the conductive contact is formed to be in direct contact with the third barrier layer...” in combination with the remaining limitations.
With regards to claim 35, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claim 35 have been found to be allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899