Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-10 and 28-30, drawn to a method of manufacturing two overlapping transistors, classified in H10D 30/6735.
II. Claims 21-27, drawn to a method of manufacturing a structure that has a first transistor existing in two other transistors and a second transistor existing in two other transistors, classified in H10D 84/856.
The inventions are independent or distinct, each from the other because:
Inventions I and II are directed to related processes. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed are not capable of use together, do not overlap in scope, and are not obvious variants because a method of manufacturing two overlapping transistors and a method of manufacturing a structure that has a first transistor existing in two other transistors and a second transistor existing in two other transistors recite different manufacturing steps and manufacture different structures. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
inventions have acquired a separate status in the art in view of their different classification,
the inventions require a different field of search (e.g. searching different class/subclasses or electronic resources, or employing different search strategies or search queries), and
the presence of a number of clarity issues (for example, in claim 21 it is unclear how a first transistor can exist in both a lower transistor and a upper transistor, it is unclear clear how a second transistor can exist in both a lower and an upper transistor, and it is unclear how a same gate electrode is made of a first gate electrode and a second gate electrode because two electrodes lose their distinctiveness when formed as one electrode).
The examiner now points out that applicant elected claims 1-10 in the response filed on May 13, 2026 and that claims 21-27 are directed to invention II which is independent or distinct from invention I, the invention elected by the applicant. Therefore, invention I directed toward claims 1-10 and 28-30 has been constructively elected by original presentation for prosecution on the merits and invention II directed toward claims 21-27 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Information Disclosure Statement
The information disclosure statements (IDS)s submitted on July 2, 2024, July 17, 2024, March 25, 2025, and August 13, 2025 were filed before the mailing of a first Office action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to because figure 2 labels the substrate with reference number 20’. Reference number 20 is understood to refer to the substrate and reference number 20’ is understood to refer to semiconductor strips. See paragraphs 18 and 24. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: the paragraphs of the specification are not consecutively numbered. The examiner notes that on page 6 paragraph number 1 follows paragraph 20. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thomas et al. (US2022/0199620).
Regarding Claim 1:
Thomas discloses a method comprising:
forming a first semiconductor channel region (forming predominantly silicon channel wires for a transistor of a first conductivity type, See fig. 1, ref. no. 151, fig. 4B, ref. nos. 410, 420, 430, 450, 460, fig. 5, ref. no. 151, 215A, paragraphs 26, 53-57 and 65-66) and a second semiconductor channel region (forming predominantly silicon channel wires for a transistor of a second conductivity type, See fig. 1, ref. no. 152, fig. 4B, ref. nos. 410, 420, 430, 450, 460, fig. 5, ref. no. 152, 215B, paragraphs 26, 53-57 and 65-66), wherein the second semiconductor channel region overlaps the first semiconductor channel region (the channel wires for the transistor of the second conductivity type are stacked above the channel wires for the transistor of the first conductivity type, See fig. 1, ref. nos. 151, 152, fig. 5, ref. nos. 151, 152, 215A, 215B);
forming a first gate dielectric (forming a gate dielectric around the channel wires for a transistor of the first conductivity type, See fig. 4B, ref. no. 470, fig. 5, ref. no. 315, paragraphs 58 and 66) on the first semiconductor channel region;
forming a second gate dielectric (forming a gate dielectric around the channel wires for a transistor of the second conductivity type, See fig. 4B, ref. no. 470, fig. 5, ref. no. 315, paragraphs 58 and 66) on the second semiconductor channel region;
forming a first dipole film and a second dipole film (forming a p-type dipole shifter material on the gate dielectric for the transistor of the first conductivity type and a n-type dipole shifter material on the gate dielectric for the transistor of the second conductivity type, See fig. 5, ref. nos. 515, 516, and paragraphs 66-67) on the first gate dielectric and the second gate dielectric, respectively;
driving in dipole dopants (annealing to diffuse the dipole dopants into the gate dielectrics, See fig. 4B, ref. no. 480, fig. 5, paragraphs 61-62 and 67) in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively;
removing the first dipole film and the second dipole film (stripping the p-type dipole shifter material and the n-type dipole shifter material, See fig. 4B, ref. no. 490, fig. 5, and paragraph 62); and
forming a gate electrode (forming a gate electrode by depositing work function metals, See fig. 4B, ref. no. 495, fig. 5, ref. nos. 510A, 510B, paragraphs 63 and 68) on both of the first gate dielectric and the second gate dielectric, wherein the gate electrode and the first gate dielectric are comprised in a first transistor (transistor of a first conductivity type, See fig. 1, 5, ref. no. 151) and the gate electrode and the second gate dielectric are comprised in a second transistor (transistor of a second conductivity type, See fig. 1, 5, ref. no. 152).
Regarding Claim 2:
Thomas discloses wherein work function layers in the gate electrode have p-type work functions (work function metals maybe p-type work function metal, See paragraphs 38 and 68) and wherein a first one of the first transistor and the second transistor is a p-type transistor (the first transistor is a PMOS transistor, See fig. 1, 5, ref. no. 151 and paragraph 26), and a second one of the first transistor and the second transistor is an n-type transistor (the second transistor is an NMOS transistor, See fig. 1, 5, ref. no. 152 and paragraph 26).
Regarding Claim 5:
Thomas discloses forming a first source/drain region aside the first semiconductor channel region (forming a source/drain region in contact with channel wires for a transistor of a first conductivity type, See fig. 1, ref. no. 106, paragraphs 26, 56, and 68); and forming a second source/drain region aside the second semiconductor channel region (forming a source/drain region in contact with channel wires for a transistor of a second conductivity type, See fig. 1, ref. no. 106, paragraphs 26, 56, and 68), wherein the second source/drain region overlaps the first source/drain region (the source/drain region for a transistor of a first conductivity type is stacked above the source/drain region for a transistor of a second conductivity type, See fig. 1, ref. nos. 106, 151, 152, fig. 5, ref. nos. 151, 152, 215A, 215B).
Regarding Claim 9:
Thomas discloses wherein the forming the first dipole film and the second dipole film comprises:
depositing the first dipole film (forming the p-type dipole shifter material on the gate dielectric for the transistor of the first conductivity type and the gate dielectric for the transistor of the second conductivity type, See fig. 5, ref. nos. 315, 515, and paragraph 66) on both of the first gate dielectric and the second gate dielectric;
removing the first dipole film from the second gate dielectric (stripping the p-type dipole shifter material from the gate dielectric for the NMOS transistor, See fig. 5, ref. nos. 315, 515, and paragraph 67); and
forming the second dipole film on the second gate dielectric (forming the n-type dipole shifter material on the gate dielectric for the NMOS transistor, See fig. 5, ref. nos. 315, 516, and paragraph 67).
Regarding Claim 10:
Thomas discloses after the first dipole film is deposited, forming a sacrificial layer to contact both of the first gate dielectric and the second gate dielectric (depositing dielectric material over the gate dielectric for the transistor of the first conductivity type and the gate dielectric for the transistor of the second conductivity type, See paragraph 66);
recessing the sacrificial layer to a level lower than the second gate dielectric (partially etching back the dielectric material to expose the p-type dipole shifter material on the gate dielectric for the transistor of the second conductivity type, See fig. 5, ref. no. 20 and paragraph 66), wherein the first dipole film is removed from the second gate dielectric after the recessing (stripping the p-type dipole shifter material from the gate dielectric for the transistor of the second conductivity type, See fig. 5, ref. nos. 315, 515, and paragraph 67), and the second dipole film is deposited after the first dipole film is removed from the second gate dielectric (forming the n-type dipole shifter material on the gate dielectric for the transistor of the second conductivity type, See fig. 5, ref. nos. 315, 516, and paragraph 67); and
removing the sacrificial layer (stripping dielectric material from the transistor structure, See fig. 5, ref. no. 520 and paragraph 67).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al. (US2022/0199620) in view of Bao et al. (US 2023/0261074).
Regarding Claim 3:
Thomas discloses the above stated method of manufacturing two overlapping transistors. Thomas also discloses wherein the first transistor is the p-type transistor (the first transistor is a p-type transistor, See paragraph 26), and the second transistor is the n-type transistor (the first transistor is a n-type transistor, See paragraph 26. The examiner notes that Thomas discloses the first transistor and the second transistor may each be p-type or n-type See paragraph 26).
Thomas does not disclose wherein the second dipole film is thicker than the first dipole film.
Bao discloses wherein the second dipole film is thicker than the first dipole film (the multilayer dipole film on the right most nanosheet device is thicker than the single layer dipole film on the second from the bottom nanosheet device, See fig. 10, ref. nos. 100, 125, 130, 145, 165 and paragraph 44).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing two overlapping transistors of Thomas to include wherein the second dipole film is thicker than the first dipole film as taught by Bao in order to adjust the voltages of the p-type transistor and the n-type transistor to desired voltages. (See Bao paragraphs 1-2 and 35.)
Regarding Claim 4:
Thomas discloses the above stated method of manufacturing two overlapping transistors. Thomas discloses wherein the first transistor is the n-type transistor (the first transistor is an n-type transistor, See paragraph 26), and the second transistor is the p-type transistor (the second transistor is a p-type transistor, See paragraph 26. The examiner notes that Thomas discloses the first transistor and the second transistor may each be p-type or n-type See paragraph 26).
Thomas does not disclose wherein the second dipole film is thinner than the first dipole film.
Bao discloses wherein the second dipole film is thinner than the first dipole film (the single layer dipole film on the second from the bottom nanosheet device is thinner than the multilayer dipole film on the right most nanosheet device, See fig. 10, ref. nos. 100, 125, 130, 145, 165 and paragraph 44).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing two overlapping transistors of Thomas to include wherein the second dipole film is thinner than the first dipole film as taught by Bao in order to adjust the voltages of the n-type transistor and the p-type transistor to desired voltages. (See Bao paragraphs 1-2 and 35.)
Regarding Claim 8:
Thomas discloses the above stated method of manufacturing two overlapping transistors.
Thomas does not disclose forming a plurality of transistors at a same level as the first transistor, wherein the forming the plurality of transistors comprises: adopting a plurality of dipole films comprising a same dipole as the first dipole film, wherein the plurality of dipole films have thicknesses different from each other, and wherein gate electrodes of the plurality of transistors are formed in common processes and have same materials.
Bao discloses forming a plurality of transistors (a plurality nanosheet devices located on a common substrate, See figs. 1, 10 ref. nos. 100, 105, paragraphs 35 and 44) at a same level as the first transistor, wherein the forming the plurality of transistors comprises: adopting a plurality of dipole films (dipole film on nanosheet device second from the bottom, dipole film on nanosheet device third from the bottom, and dipole film on the top nanosheet device, See fig. 10, ref. no. 130, 145, 165, and paragraph 44) comprising a same dipole as the first dipole film (the first dipole material, the second dipole material, and the third dipole material can be the same material, See paragraphs 39 and 42), wherein the plurality of dipole films have thicknesses different from each other (the dipole film on the top nanosheet device is thickest because three dipole films are deposited on the top nanosheet device, the dipole film on third from the bottom nanosheet device is the second thickest because two dipole films are deposited on the nanosheet device second from the bottom, and the dipole film on the nanosheet device second from the bottom is the thinnest because on dipole film is deposited on the nanosheet device second from the bottom, See fig. 10, ref. nos. 130, 145, 165, and paragraph 44), and wherein gate electrodes of the plurality of transistors are formed in common processes and have same materials (gate metal layer is formed around the plurality of nanosheet devices, See fig. 13, ref. no. 235 and paragraph 37).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing two overlapping transistors of Thomas to include forming a plurality of transistors at a same level as the first transistor, wherein the forming the plurality of transistors comprises: adopting a plurality of dipole films comprising a same dipole as the first dipole film, wherein the plurality of dipole films have thicknesses different from each other, and wherein gate electrodes of the plurality of transistors are formed in common processes and have same materials as taught by Bao in order to reduce manufacturing costs by manufacturing multiple transistors at the same time.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al. (US2022/0199620) in view of Liang et al. (US 2024/0105728).
Regarding Claim 6:
Thomas discloses the above stated method of manufacturing two overlapping transistor.
Thomas does not disclose forming a first contact plug overlying and electrically coupling to the first source/drain region; and forming a second contact plug underlying and electrically coupling to the second source/drain region.
Liang discloses a first contact plug overlying (first drain via, first drain via, first drain connection portions, See fig. 5B, ref. nos. 532, 533, 542 and paragraph 76) and electrically coupling to a source/drain region (drain, See fig. 5B, ref. no. 510); and forming a second contact plug underlying (second drain via and second drain connection portion, See fig. 5B, ref. nos. 502, 503 and paragraph 76) and electrically coupling to a source/drain region (drain, See fig. 5B, ref. no. 510).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing two overlapping transistors of Thomas to include a first contact plug overlying and electrically coupling to a source/drain region and electrically coupling to a source/drain region as taught by Liang so that the transistors can be connected to components on front side and back sides of the transistors. (The examiner notes that in the combination of Thomas and Liang the first drain via, first drain via, first drain connection portions will overlay the source/drain region of the transistor of the first conductivity type and be electrically coupled to the source/drain region for the first conductivity type through the source/drain for the transistor of the second conductivity type and the second drain via and second drain connection portion will underly the source/drain region of the transistor of the second conductivity type and be electrically coupled to the source/drain region for the transistor of the second conductive type through the source/drain region for the transistor of the first conductivity type.)
Regarding Claim 7:
Thomas discloses wherein the first transistor and the second transistor are of opposite conductivity types (the transistor of the first conductivity type and the transistor of the second conductivity type have complementary conductivity type, See paragraph 26).
Claims 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al. (US2022/0199620) in view of Xie et al. (US 2023/0125316).
Regarding Claim 28:
Thomas discloses a method comprising:
forming a lower transistor (forming a transistor of a first conductivity type, See fig. 1, ref. no. 151, fig. 4B, paragraphs 26 and 53-68) comprising:
a first channel region (predominantly silicon channel wires for the transistor of the first conductivity type, See fig. 1, ref. no. 151, fig. 4B, ref. nos. 410, 420, 430, 450, 460, paragraphs 26, 53-57);
a first gate dielectric on the first channel region (a gate dielectric around the channel wires for the transistor of the first conductivity type, See fig. 4B, ref. no. 470, fig. 5, ref. no. 315, paragraphs 58 and 65-66); and
a first source/drain region (a source/drain region in contact with channel wires for the transistor of the first conductivity type, See fig. 1, ref. no. 106, paragraphs 26, 56, and 68) connecting to the first channel region; and
forming an upper transistor (forming a transistor of a second conductivity type, See fig. 1, ref. no. 152, fig. 4B, paragraphs 26 and 53-68) comprising:
a second channel region (predominantly silicon channel wires for the transistor of the second conductivity type, See fig. 1, ref. no. 152, fig. 4B, ref. nos. 410, 420, 430, 450, 460, paragraphs 26, 53-57) overlapping the first channel region;
a second gate dielectric on the second channel region (a gate dielectric around the channel wires for the transistor of the second conductivity type, See fig. 4B, ref. no. 470, fig. 5, ref. no. 315, paragraphs 58 and 65-66); and
a second source/drain region (a source/drain region in contact with channel wires for the transistor of the second conductivity type, See fig. 1, ref. no. 106, paragraphs 26, 56, and 68) connecting to the second channel region, wherein the second source/drain region overlaps the first source/drain region (the source/drain region for a transistor of a first conductivity type is stacked above the source/drain region for a transistor of a second conductivity type, See fig. 1, ref. nos. 106, 151, 152, fig. 5, ref. nos. 151, 152, 215A, 215B), and
depositing a common gate electrode (gate electrode formed around gate electric for the transistor of the first conductivity type and the transistor of the second conductivity type, See fig. 1, ref. no. 110, fig. 4B, ref. no. 495 and paragraphs 38 and 63) that continuously extends from a first level lower than the first channel region to a second level higher than the second channel region (the gate electrode continuously extends from below the bottom channel wire for the transistor of the first conductivity type to above the top channel wire for the transistor of the second conductivity type, See fig. 1, ref. nos. 110, 151, 152).
Thomas does not disclose wherein the first source/drain region and the second source/drain region have opposite conductivity types.
Xie discloses the first source/drain region and the second source/drain region have opposite conductivity types (the first source/drain region is doped to have an opposite conductivity of the second source/drain region, See fig. 11A, ref. nos. 32, 36 and paragraphs 57-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing two overlapping transistors of Thomas to include the first source/drain region and the second source/drain region have opposite conductivity types as taught by Xie in order to reduce resistances of the transistor of the first conductivity and the transistor of the second conductivity type.
Regarding Claim 29:
Thomas discloses wherein the common gate electrode is deposited as comprising: a lower portion (the portion of the gate electrode predominantly silicon channel wires for the transistor of the second conductivity type, See fig. 1, ref. nos. 110, 151) acting as a first gate electrode of the lower transistor; and an upper portion (the portion of the gate electrode predominantly silicon channel wires for the transistor of the second conductivity type, See fig. 1, ref. nos. 110, 151) acting as a second gate electrode of the upper transistor, wherein no interface is formed between the lower portion and the upper portion (there is no interface between the lower portion and the upper portion because the gate electrode is made of a single metal, See paragraph 38).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al. (US2022/0199620) in view of Xie et al. (US 2023/0125316) further in view of Hong et al. (US 2023/0343845).
Regarding Claim 30:
The above stated combination of Thomas and Xie discloses the above stated method of manufacturing two overlapping transistor. The examiner notes that Thomas discloses a common gate electrode (See fig. 1, ref. no. 110 and paragraph 38).
The above stated combination of Thomas and Xie does not disclose wherein the common gate electrode comprises p-type work function layers encircling each of the first gate dielectric and the second gate dielectric.
Hong disclose lower channel layers of a nanosheet transistor surrounded by a lower gate dielectric and a lower work function metal and upper channel layer of a nanosheet transistor surround by an upper gate dielectric and an upper work function metal (See fig. 1C, ref. nos. 110, 115D, 115F, 120, 120D, 120F, and paragraphs 39-40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing two overlapping transistors to include lower channel layers of a nanosheet transistor surrounded by a lower gate dielectric and a lower work function metal and upper channel layer of a nanosheet transistor surround by an upper gate dielectric and an upper work function metal as taught by Hong in order to control threshold voltage of the transistor of the first conductivity type and the transistor of the second conductivity type. (See Hong paragraph 43.)
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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