DETAILED ACTION
This Office action responds to the patent application no. 18/505,024 filed on November 08, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show “the first reference voltage line is electrically connected to the first sub-pixel, and the second reference voltage line is electrically connected to the second sub-pixel” as described in the paragraph (¶) [0028] of the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the first reference voltage line is electrically connected to the first sub-pixel, and the second reference voltage line is electrically connected to the second sub-pixel” must be shown or the feature(s) canceled from Claim 19. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim hereinafter) (US 2023/0069761) in view of Choi et al. (Choi hereinafter) (US 2022/0085071) and further in view of Jeon (US 9,030,618).
Regarding Claims 1-6:
Kim (see FIGs. 2, 7, 9, 12, 13) teaches {1} a display apparatus comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel emitting light of different colors from one another, each of the first to third sub-pixels comprising: a substrate 10; a driving transistor M1/M11 arranged above the substrate and comprising a semiconductor layer A11 and a driving gate electrode G11, the semiconductor layer comprising a driving active region; a first capacitor comprising a first capacitor electrode VDLa/VSLa/CE2b and a second capacitor electrode MIL1/MIL2/CE1, and the second capacitor electrode being arranged on a same layer as the semiconductor layer; and a display element LED1/LED2/LED3 electrically connected to the second capacitor electrode.
Kim (see ¶ [0057], [0088], [0104], [107], [0166], [0172]) teaches “each pixel may emit red, green, or blue light”; “The third transistor M3 may be an initialization transistor and/or a sensing transistor … may be connected to a sensing line ISL”; “the scan line and the control line CL may extend in the x-direction … a second driving voltage line VDLb and a second common voltage line VSLb may each extend in the x-direction”; “A channel area of the driving transistor T1 may be disposed between the first area 1131-1 and the second area 1131-2 of the first semiconductor 1131 … has a bent structure and may have an omega (Ω) shape”; “The first intermediate layer MIL1 and/or the second intermediate layer MIL2 may be arranged at (e.g., in or on) the same layer as that of the semiconductor layer, and may include the same or substantially the same material as that of the semiconductor layer … may include an oxide semiconductor”; “the first intermediate layer MIL1 and/or the second intermediate layer MIL2 may be arranged at … the same layer as that of the second sub-electrode CE2t of the first storage capacitor Cst1”.
However, Kim does not explicitly teach {1} a driving shield layer arranged between the substrate and the driving active region; the first capacitor electrode being arranged on a same layer as the driving shield layer; at least one of a length of the driving active region of the first sub-pixel, a length of the driving active region of the second sub-pixel, and a length of the driving active region of the third sub-pixel is different from other ones of the lengths; {2} each of the first to third sub-pixels further comprises a first scan line 161/162/162-1 arranged on the same layer as the driving shield layer and extending in a first direction, and wherein the driving active region extends in a second direction crossing the first direction; and {3} at least one of a length of the driving gate electrode of the first sub-pixel, a length of the driving gate electrode of the second sub-pixel, and a length of the driving gate electrode of the third sub-pixel in the second direction is different from other ones of the lengths; {4} the length of the driving active region of the second sub-pixel is greater than the length of the driving active region of the first sub-pixel and the length of the driving active region of the third sub-pixel; {5} the length of the driving active region of the first sub-pixel and the length of the driving active region of the third sub-pixel are a same as each other; and {6} the first sub-pixel is a red pixel, the second sub-pixel is a green pixel, and the third sub-pixel is a blue pixel.
Choi (see ¶ [0055]) teaches “the lower layer 120 made of a conductive metal or a semiconductor material having a conductive characteristic … may block external light so that the external light does not reach a channel region 133 of the semiconductor layer 130 to reduce a leakage current and characteristic deterioration of the channel region 133”.
Jeon (see FIGs. 9 and 10 and col.1/ll.52-55 and col.10/ll.50-67) teaches “The size of the driving TFT may vary with the length of the a channel region in which a driving gate electrode and a driving semiconductor layer overlap with each other by adjusting a length of the driving gate electrode” and “Due to flexion of the flexible display panel 10 … pixel brightness is decreased or increased accordingly by adjusting driving TFT sizes of the pixels according to pixel positions, as each driving TFT drives a separate pixel” and LR = LB < LG2/LG3.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kim to include the teaching of Choi to form a light-blocking or light-shield layer underneath all the transistors to reduce leakage current and to utilize the lower conductive layer for interconnection purpose, such as a capacitor electrode and a scan line to simplify the manufacturing processes and to further include the teaching of Jeon to have different length of the driving channel for different sub-pixels and to specify the length of the driving gate electrode and the channel of the green sub-pixels being longer than those of the red and blue sub-pixels to maintain the same brightness everywhere in the display panel.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim hereinafter) (US 2023/0069761) in view of Choi et al. (Choi hereinafter) (US 2022/0085071) and further in view of Jeon (US 9,030,618) as applied to claim 1 above, and further in view of Park et al. (Park hereinafter) (US 2023/0141774).
Regarding Claims 7-10:
Kim in the device of Choi in view of Jeon does not explicitly teach {7} each of the first to third sub-pixels further comprises: an initialization voltage line arranged on the same layer as the driving shield layer; and an initialization transistor connected to the initialization voltage line, wherein the initialization voltage line comprises a first initialization voltage line and a second initialization voltage line spaced apart from each other, and wherein the first initialization voltage line is electrically connected to the initialization transistor of one sub-pixel among the first to third sub-pixels, and the second initialization voltage line is electrically connected to the initialization transistors of other two sub-pixels among the first to third sub-pixels; {8} a magnitude of a first initialization voltage transferred through the first initialization voltage line is different from magnitude of a second initialization voltage transferred through the second initialization voltage line; {9} each of the first to third sub-pixels further comprises: a reference voltage line arranged on the same layer as the driving shield layer; and a reference voltage transistor connected to the reference voltage line, wherein the reference voltage line comprises a first reference voltage line and a second reference voltage line spaced apart from each other; and {10} the first reference voltage line is electrically connected to the reference voltage transistor of one sub-pixel among the first to third sub-pixels, and the second reference voltage line is electrically connected to the reference voltage transistors of other two sub-pixels among the first to third sub-pixels.
Park (see FIGs. 11-14 and ¶ [0106], [0140]-[0142]) teaches three initialization voltage lines 173/175/175-1 and two reference voltage lines 174-1/174-2 and “the first reference voltage line 174-1 and the … initialization voltage line 175-1 extend in a first direction (hereinafter also referred as a horizontal direction”; “the first initialization voltage line 173 extends in the first direction”; “the second reference voltage line 174-2 extends in the first direction”; “the second initialization voltage line 175 extends in the first direction”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Kim in the device of Choi in view of Jeon to further include the teaching of Park to add a second initialization voltage line and to connect different initialization voltage line with different voltage to the initialization transistor in different pixel circuits to allow more precise control and faster initialization and improved stability of the display panel and to form first and second reference voltage lines and to connect different reference voltage line to the reference transistor in different pixel circuits to allow more precision control for better image quality and improved stability and signal integrity.
Claims 11-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (Choi hereinafter) (US 2022/0085071) in view of Jeon (US 9,030,618) and further in view of Hwang (US 2015/0207094).
Regarding Claims 11-16 and 20:
Choi (see FIGs. 7, 8, 10) teaches {11} a display apparatus comprising: a substrate 110; a first sub-pixel PX1 comprising a first pixel circuit comprising a first driving transistor T1 and a first initialization transistor T3, the first driving transistor being arranged above the substrate and comprising a first semiconductor layer 130, the first semiconductor layer comprising a first driving active region 133 and a first driving gate electrode 140; a second sub-pixel PX2 comprising a second pixel circuit comprising a second driving transistor T1 and a second initialization transistor T3, the second driving transistor being arranged above the substrate and comprising a second semiconductor layer 130, the second semiconductor layer comprising a second driving active region 133 and a second driving gate electrode 140; and a horizontal driving voltage line 148, extending in a first direction, and electrically connected to the first sub-pixel and the second sub-pixel.
Choi (see ¶ [0057], [0113], [0114]) teaches “The semiconductor layer 130 may include one of an oxide semiconductor”; “The initialization voltage transmitting portion 144 is a structure for connecting an initialization voltage line 173 formed per pixel columns”; “The horizontal driving voltage line 148 is disposed between adjacent pixels PX in the row direction, and is electrically connected to the driving voltage line 175 through a contact opening 57 for each adjacent subpixel PX1, PX2, or PX3 in the column direction”.
However, Choi does not explicitly teach {11} a horizontal driving voltage line arranged between the substrate and the first semiconductor layer; a size of the first driving gate electrode is different from a size of the second driving gate electrode; {12} a length of the first driving gate electrode in a second direction crossing the first direction is different from a length of the second driving gate electrode in the second direction; {13} a length of the first driving active region is different from a length of the second driving active region; {14} a third sub-pixel comprising a third pixel circuit comprising a third driving transistor and a third initialization transistor, the third driving transistor being arranged above the substrate and comprising a third semiconductor layer, the third semiconductor layer comprising a third driving active region and a third driving gate electrode, wherein a size of the third driving gate electrode is a same as the size of the first driving gate electrode; {15} the first sub-pixel is a red pixel, the second sub-pixel is a green pixel, and the third sub-pixel is a blue pixel; {16} a length of the second driving active region is greater than a length of the first driving active region and a length of the third driving active region; and {20} the first semiconductor layer comprises an oxide semiconductor material.
Jeon (see FIG. 10 and col.1/ll.52-55 and col.10/ll.50-67) teaches “The size of the driving TFT may vary with the length of the a channel region in which a driving gate electrode and a driving semiconductor layer overlap with each other by adjusting a length of the driving gate electrode” and “Due to flexion of the flexible display panel 10 … pixel brightness is decreased or increased accordingly by adjusting driving TFT sizes of the pixels according to pixel positions, as each driving TFT drives a separate pixel” and LR = LB < LG2/LG3.
Hwang (see FIG. 11 and ¶ [0121]) teaches “the driving voltage line 112 … arranged between the semiconductor layer 131 and the substrate 110”
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Choi to include the teaching of Jeon to have different size or length of the driving gate electrode and the channel for different sub-pixels and to specify the length of the driving gate electrode and the channel of the green sub-pixels being longer than those of the red and blue sub-pixels to maintain the same brightness everywhere in the display panel and to further include the teaching of Hwang to utilize the lower layer 120 between the semiconductor layer and substrate as another metallization layer for interconnection purpose, such as a horizontal driving voltage line and initialization voltage lines and reference voltage lines besides as a light-blocking layer to simplify the manufacturing processes.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (Choi hereinafter) (US 2022/0085071) in view of Jeon (US 9,030,618) and further in view of Hwang (US 2015/0207094) as applied to claim 16 or 11 above, and further in view of Park et al. (Park hereinafter) (US 2023/0141774).
Regarding Claims 17-19:
Choi in the device of Jeon in view of Hwang does not explicitly teach {17} a first initialization voltage line and a second initialization voltage line arranged between the substrate and the first semiconductor layer and extending in the first direction, wherein the first initialization voltage line is electrically connected to the second initialization transistor, and the second initialization voltage line is electrically connected to the first initialization transistor and the third initialization transistor; {18} a first initialization voltage line and a second initialization voltage line arranged between the substrate and the first semiconductor layer and extending in the first direction, wherein the first initialization voltage line is electrically connected to the second initialization transistor, and the second initialization voltage line is electrically connected to the first initialization transistor; and {19} a first reference voltage line and a second reference voltage line arranged between the substrate and the first semiconductor layer and extending in the first direction, wherein the first reference voltage line is electrically connected to the first sub-pixel, and the second reference voltage line is electrically connected to the second sub-pixel.
Park (see FIGs. 11-14 and ¶ [0106], [0140]-[0142]) teaches three initialization voltage lines 173/175/175-1 and two reference voltage lines 174-1/174-2 and “the first reference voltage line 174-1 and the … initialization voltage line 175-1 extend in a first direction (hereinafter also referred as a horizontal direction”; “the first initialization voltage line 173 extends in the first direction”; “the second reference voltage line 174-2 extends in the first direction”; “the second initialization voltage line 175 extends in the first direction”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Choi in the device of Jeon in view of Hwang to further include the teaching of Park to add a second initialization voltage line and to connect different initialization voltage line to initialization transistor in different pixel circuits to allow more precise control and faster initialization and improved stability of the display panel and to add a second reference voltage line and to connect different reference voltage line to reference transistor in different pixel circuits to allow more precision control for better image quality and improved stability and signal integrity.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814