DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: claim 1 recites “wherein the forming of the second metal interconnections and the third metal interconnections comprising:”. The underlined is grammatically incorrect. Appropriate correction is required. Suggestion: “wherein the forming of the second metal interconnections and the third metal interconnections comprises:”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20200090944 A1 (Lee).
Re claim 1, Lee teaches a method of forming semiconductor device, comprising:
providing a substrate (substrate 300);
forming a first interconnect layer on the substrate, the first interconnect layer comprising a first dielectric layer (second insulating layer 480/third insulating layer 510) around a plurality of first metal interconnections (first contact plug 530/source lines 500);
forming a second interconnect layer on the first interconnect layer, the second interconnect layer comprising a second dielectric layer (first etch stop layer 540/fourth insulating layer 550) around a plurality of second metal interconnections (first conductive patterns 660) and a plurality of third metal interconnections (second conductive patterns 670), wherein the forming of the second metal interconnections and the third metal interconnections comprising:
forming a plurality of first mask patterns (pattern made by first openings 590 Fig. 17) on the second dielectric layer, the first mask patterns being arranged with a first pitch;
forming a plurality of second mask patterns (pattern made by openings 565 Fig. 18) on the first mask patterns, the second mask patterns being arranged with a second pitch which is greater than the first pitch (Figs. 17-18);
performing an etching process through the second mask patterns and the first mask patterns (Figs. 19-20), to form a plurality of first openings throughout the second dielectric layer and a plurality of second openings disposed within the second dielectric layer; and
forming the second metal interconnections and the third metal interconnections in the first openings and the second openings (Fig. 21); and
forming a third interconnect layer on the second interconnect layer, the third interconnect layer comprising a third dielectric layer (second etch stop layer 710/fifth insulating layer 720/sixth insulating layer 910) around a plurality of first magnetic tunneling junction (MTJ) structures (MTJ structures 885).
Re claim 2, Lee teaches wherein a portion of the first metal interconnections is electrically connected to a source region disposed in the substrate (500 source lines).
Re claim 3, Lee teaches wherein a width of each of the second metal interconnections is greater than a width of each of the third metal interconnections (see annotated Fig. 21).
PNG
media_image1.png
624
660
media_image1.png
Greyscale
Re claim 4, Lee teaches wherein the second metal interconnections formed in the second openings are electrically connected to a source region disposed in the substrate (indirectly electrically connected to source regions of the transistors Fig. 21).
Re claim 9, Lee teaches wherein the second metal interconnection and a portion of the third metal interconnections are monolithic (Fig. 21).
Allowable Subject Matter
Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896