DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/08/2023 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation "the insulating layer" in line 4. There is insufficient antecedent basis for this limitation in the claim. NOTE: In line 2, the Applicant claims “an insulator layer” instead of an insulating layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 9,1 0, 13 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 2010/0187694).
Regarding claim 1, Yu teaches a semiconductor structure in figs. 1-8 comprising a silicon-on-insulator (SOI) substrate (refer to 112 as labeled in fig. 7 and par. 15), comprising:
a silicon-on-insulator substrate (refer to SOI 112), which comprises a silicon layer (refer to silicon layer of SOI 112) and an insulator layer (refer to a buried insulator layer of SOI 112) stacked from bottom to top (see par. 15 and fig. 7);
a phosphosilicate glass (PGS) (refer to 116; see par. 19) located on the insulating layer (refer to the buried insulator layer of SOI 112); and
a fluorosilicate glass (FSG) (refer to 130; see par. 29) located on the phosphosilicate glass (116).
Regarding claim 2, Yu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Yu teaches a thickness of the phosphosilicate glass (116) is smaller than a thickness of the fluorosilicate glass (130) (see fig. 7).
Regarding claim 5, Yu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Yu teaches a transistor (113; see par. 17) located under the silicon layer (refer to the silicon layer of SOI 112) (see fig. 8).
Regarding claim 9, Yu teaches a method for forming a semiconductor structure including a silicon-on-insulator (SOI) substrate in figs. 1-8, comprising:
providing a silicon-on-insulator substrate (refer to SOI 112 as labeled in fig. 7 and par. 15), wherein the silicon-on-insulator substrate (refer to 112) comprises a silicon layer (refer to a silicon layer of 112) and an insulating layer (refer to a buried insulator of SOI 112) stacked from bottom to top (see fig. 7);
forming a phosphosilicate glass (PGS) (refer to 116; see par. 19) on the insulating layer (refer to the buried layer of SOI 112); and
forming a fluorosilicate glass (FSG) (refer 130; see par. 29) on the phosphosilicate glass (refer to 116).
Regarding claim 10, Yu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Yu teaches a thickness of the phosphosilicate glass (116) is smaller than a thickness of the fluorosilicate glass (130) (see fig. 7).
Regarding claim 13, Yu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Yu teaches a transistor (113; see par. 17) located under the silicon layer (refer to the silicon layer of SOI 112) (see fig. 8).
Regarding claim 17, Yu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Yu teaches after the fluorosilicate glass is formed, the method further comprises performing a planarization step to the fluorosilicate glass (see fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2010/0187694) as applied to claim 1 above, and further in view of Kim (US 20180130886).
Regarding claim 6, Yu teaches all the limitations of the claimed invention for the same reasons as set forth above.
Yu does not explicitly show the transistor comprises a source region and a drain region located in the silicon layer, and a gate located under the silicon layer.
Fig. 1 of Kim teaches the same field of an endeavor wherein the transistor (30) comprises a source region (20) and a drain region (20) located in the silicon layer, and a gate (30) located under the silicon layer (refer to rear view by looking from SOI 11 to layer 72).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the transistor comprises a source region and a drain region located in the silicon layer, and a gate located under the silicon layer as shown in fig. 1 of Kim in the teaching of Yu because it is commonly known in the art that a source, a drain terminals and gate terminal of a MOSFET are crucial for its operation.
Regarding claim 7, Yu and Kim teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 8 of Yu teaches a dielectric layer (114) located under the silicon layer (refer to the silicon layer of SOI substrate 112).
Regarding claim 8, Yu and Kim teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 8 of Yu teaches a plurality of contact structures (118) located in the dielectric layer (116) and electrically connecting the source region and the drain region (refer to source/drain of gate 113).
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2010/0187694) as applied to claim 9 above, and further in view of Kim (US 20180130886).
Regarding claim 14, Yu teaches all the limitations of the claimed invention for the same reasons as set forth above.
Yu does not explicitly show the transistor comprises a source region and a drain region located in the silicon layer, and a gate located under the silicon layer.
Fig. 1 of Kim teaches the same field of an endeavor wherein the transistor (30) comprises a source region (20) and a drain region (20) located in the silicon layer, and a gate (30) located under the silicon layer (refer to rear view by looking from SOI 11 to layer 72).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the transistor comprises a source region and a drain region located in the silicon layer, and a gate located under the silicon layer as shown in fig. 1 of Kim in the teaching of Yu because it is commonly known in the art that a source, a drain terminals and gate terminal of a MOSFET are crucial for its operation.
Regarding claim 15, Yu and Kim teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 8 of Yu teaches a dielectric layer (114) located under the silicon layer (refer to the silicon layer of SOI substrate 112).
Regarding claim 16, Yu and Kim teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 8 of Yu teaches a plurality of contact structures (118) located in the dielectric layer (116) and electrically connecting the source region and the drain region (refer to source/drain of gate 113).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation recites “wherein the insulating layer comprises a silicon oxide layer and a silicon oxynitride layer stacked from bottom to top.” Claim 4 includes all the limitations of claim 3.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation recites “wherein the insulating layer comprises a silicon oxide layer and a silicon oxynitride layer stacked from bottom to top.” Claim 12 includes all the limitations of claim 11.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation recites “wherein during the planarization step, a plurality of ions are diffused into the fluorosilicate glass from a polishing solution in the planarization step and blocked by the phosphosilicate glass.” Claim 19 includes all the limitations of claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818