DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communication dated 04/08/2026.
Claims 1-2, 4-12, and 14-22 are pending in this application.
Claims 3, and 13 have been cancelled.
Remarks
2. Applicants’ arguments have been fully considered. Those with respect to the prior arts of Ishino et al. (US 2007/0181991), and Strong et al. (US 2021/0082825) are persuasive. However, those with respect to Chandrasekaran’s teaching (US 2009/0321939) are not.
Specifically, with respect to Chandrasekaran, Applicants argued (Applicant’s Remarks page 10):
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This is not agreed.
As shown in fig. 3, and discussed a para. 0025, the dies 320, 330 of Chandrasekaran are flip-chip dies having active circuitry on the sides facing the substrate 210. Accordingly, the back surfaces of the dies 320, 330 are the top sides facing the interconnect die 270, and the interconnect die 270 is bonded to the back surfaces of the (first) dies 320 and the (second) die 330.
Applicant further argued (Applicant’s Remarks page 10):
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As shown in fig. 3 of Chandrasekaran, the interconnect die 240 comprises a first surface (lower surface facing dies 320, 330) including a connectivity region (region comprising connectivity contact pads 371). The connectivity region is directly bonded to terminals (contact pads 381) of the first plurality of through-die vias 373 exposed at the back surface of the first die 320 and terminals of a second plurality of through-die vias 373 exposed at a back surface of the second die 330 (through-die vias 373 of the first die 320 and the second die 330 are physically exposed at least to the connectivity contact pads 371 as well as electrically exposed to the pads 371 and the TSV 270 of the interconnect die 240).
Applicant also argued (Applicant’s Remarks page 10):
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Though the interconnect line 272 of Chandrasekaran is located on the top side of the bridge die 240 opposite to the bonding bottom surface, Chandrasekaran does disclose the claimed a first surface (lower surface facing dies 320, 330) including a connectivity region (region comprising connectivity contact pads 371) as discussed above.
Claim Rejection – Non-Statutory Double Patenting
3. Claims 1, 2, 8, 9, 14, 15, 17, and 18 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1, 2, 8, 9, 13, 15, 17, and 18, respectively, of U.S. Patent No. 11,830,817.
Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one of ordinary skill in the art at the time of the invention was made that the claims of the Patent recite all claimed limitations of the instant application. The claims of the instant application are merely describing the limitations of the Patent in different ways, and they are obviously anticipated by the claims of the Patent.
See the Office Action of 08/13/2025 for details.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 8, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chandrasekaran (US 2009/0321939)
Regarding claim 1, Chandrasekaran discloses a semiconductor package comprising:
a first die 320 (see fig. 3);
a second die 330; and
an interconnect die 240 having a first surface (lower surface facing dies 320, 330) including a connectivity region (region comprising connectivity contact pads 371), wherein the connectivity region is directly bonded to terminals (contact pads 381) of a first plurality of through-die vias 373 exposed at a back surface of the first die 320 and terminals of a second plurality of through-die vias 373 exposed at a back surface of the second die 330 (through-die vias 373 of the first die 320 and the second die 330 are physically exposed at least to the connectivity contact pads 371 as well as electrically exposed to the pads 371 and the TSV 270 of the interconnect die 240). See also the above remarks.
Regarding claim 2, Chandrasekaran discloses the semiconductor package of claim 1, wherein the first die 320 includes a first die pad region (to which solder balls bonded, see fig. 3) on a first surface of a first substrate (substrate forming the die 320), the first plurality of through-die vias connecting the first die pad region to a second surface of the first substrate; and
wherein the second die 330 includes a second die pad region (connected to solder balls) on first a surface of a second substrate (substrate forming the die 330), the second plurality of through-die vias 373 connecting the second die pad region to a second surface of the second substrate.
Regarding claim 4, Chandrasekaran discloses the semiconductor package of claim 1, wherein the interconnect die 240 is hybrid bonded to the first die 320 and the second die 330, and wherein the interconnect die receives power from one or more of the first plurality of through-die vias 373 and the second plurality of through-die vias 373 (the interconnect die must be provided with power in order to operate, and fig. 3 shows the only mean for external connections, such as for power supply, is through solder balls at the bottom of the component 210 and supplied through through-die vias 373).
Regarding claim 5, Chandrasekaran discloses the semiconductor package of claim 4, wherein the first die 320, the second die 330, and the interconnect die 240 are system-on-a-chip dies, and wherein one or more of the system-on-a-chip dies receives power from one or more copper vias 373 etched in a dielectric layer included in one of the first die 320 and second die 330. See fig. 3, and the rejection of claim 2.
Regarding claim 6, Chandrasekaran discloses the semiconductor package of claim 1, wherein the interconnect die 240 includes active functional circuit blocks and die-to-die connections. See para. 0023.
Regarding claim 7, Chandrasekaran discloses the semiconductor package of claim 1, wherein the connectivity region comprises a back end of line (BEOL) structure. See fig. 3.
Regarding claim 8, Chandrasekaran discloses an apparatus comprising:
a component 210 (see fig. 3); and
a semiconductor package 300 operatively connected to the component 210, the semiconductor package 300 comprising:
a first die 320;
a second die 330; and
an interconnect die 240 having a first surface (lower surface facing dies 320, 330) including a connectivity region (region comprising connectivity contact pads 371), wherein the connectivity region is directly bonded to terminals (contact pads 381) of a first plurality of through-die vias 373 exposed at a back surface of the first die 320 and terminals of a second plurality of through-die vias 373 exposed at a back surface of the second die 330 (through-die vias 373 of the first die 320 and the second die 330 are physically exposed at least to the connectivity contact pads 371 as well as electrically exposed to the pads 371 and the TSV 270 of the interconnect die 240),
wherein the interconnect die 240 is active (see para. 0028), and wherein the first die 320 and the second die 330 receive power from the component 210 (the first die and second die must be provided with power in order to operate, and fig. 3 shows the only mean for external connections, such as for power supply, is through solder balls at the bottom of the component 210). See also the above remarks.
Regarding claim 9, Chandrasekaran discloses the apparatus comprising all claimed limitations. See the rejection of claim 2.
Regarding claim 10, Chandrasekaran discloses the apparatus of claim 9, wherein the interconnect die includes one or more logic gates. See para. 0023.
Regarding claims 11-12, Chandrasekaran discloses the apparatus comprising all claimed limitations. See the rejection of claims 4, 5, respectively.
Regarding claim 15, Chandrasekaran discloses a method of creating interconnects between dies 320, 330 (see fig. 3) using a cross-over die 240 and through-die vias 270, 373, the method comprising:
stacking an interconnect die 240 face-down on respective back surfaces of a first die 320 and a second die 330, wherein the interconnect die 240 has a face-down surface including a connectivity region (region comprising connectivity contact pads 371 (connectivity region 371 for short)); and
bonding the connectivity region 371 of the interconnect die 240 to terminals (contact pads 381) of a first plurality of through-die vias 373 exposed at a back surface of the first die 320 and terminals of a second plurality of through-die vias 373 exposed at a back surface of the second die 330 (through-die vias 373 of the first die 320 and the second die 330 are physically exposed at least to the connectivity contact pads 371 as well as electrically exposed to the pads 371 and the TSV 270 of the interconnect die 240), wherein the connectivity region 371 is directly bonded to terminals (contact pads 381) of the first plurality of through-die vias 373 in the first die 320 and the terminals (contact pads 381) of the second plurality of through-die vias 373 in the second die 330.
Regarding claim 17, Chandrasekaran discloses the method of claim 15, wherein stacking the interconnect die 240 face-down on respective back surfaces of the first die 320 and the second die 330 includes aligning a first plurality of die pads 371 of the interconnect die 240 for connection to the first plurality of through-die vias 373 and a second plurality of die pads 371 of the interconnect die 240 for connection to the second plurality of die pads. See fig. 3.
Regarding claim 19, Chandrasekaran discloses the method comprising all claimed limitations. See the rejection of claims 4-5.
Regarding claim 20, Chandrasekaran discloses the method of claim 15, wherein the interconnect die 240 includes fabricated redistribution layer structures that implement communication pathways between the first die and the second die. See paras. 0023-0028.
Regarding claim 21, Chandrasekaran discloses the apparatus of claim 8, wherein the connectivity region comprises a back end of line (BEOL) structure. See fig. 3.
Regarding claim 22, Chandrasekaran discloses the semiconductor package of claim 4, wherein power delivered to one or more of the first die and the second die is directed to the interconnect die by one or more of the first plurality of through-die vias and the second plurality of through-die vias. See the rejection of claims 4, 5.
Claim Rejections - 35 U.S.C. § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chandrasekaran (US 2009/0321939) in view of Strong et al. (US 2021/0082825)
Regarding claim 14, Chandrasekaran discloses the apparatus comprising all claimed limitations as discussed above, except for wherein a third die is coupled to the first die using a third plurality of through-die vias in the first die; and
wherein a fourth die is coupled to the second die using a fourth plurality of through-silicon vias in the second die.
Strong discloses an apparatus, shown in fig. 5, comprising a first die 180-1, a second die 180-2, a bridge die 3502 bridging the first die 180-1 and the second die 180-2, and
wherein a third die 3501 is coupled to the first die 1801 using a third plurality of through-die vias 342 in the first die 180-1; and
wherein a fourth die 350-2 is coupled to the second die 180-2 using a fourth plurality of through-silicon vias 342 in the second die 1802.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Chandrasekaran to further include a third die and a fourth die connecting respectively to the first die and the second die, as that/those taught by Strong, thereby to increase the functions, and hence the performance of the apparatus.
Regarding claim 18, Chandrasekaran/Strong discloses the method of claim 15, comprising all claimed limitations. See the rejection of claim 14.
Allowable Subject Matter
8. Claim 16 is allowable.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed method (in addition to the other limitations in the claim) further comprising, prior to stacking the interconnect die, removing a portion of the back of the first die and the second die to expose the first plurality of through-die vias and the second plurality of through-die vias.
Conclusion
9. THIS ACTION IS MADE FINAL. A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on 9:00AM - 5:00PM If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is (571)273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/
Primary Examiner, Art Unit 2818
May 23, 2026
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