DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The amendment filed on July 27th, 2026 has been acknowledged. By this amendment, claims 67, 69, 73, 76, 81, 83-85, 89, 94, 97, 99, 103, 104, 106, 113, and 114 have been amended, claims 1-60, 64, 66, 68, 71, 72, 74, 75, 77-80, 82, 86-88, 93, 96, 98, 101, 102, 105, 107-110, 112, and 116-118 have been cancelled. Accordingly, claims 61-63, 65, 67, 69, 70, 73, 76, 81, 83-85, 89-92, 94, 95, 97, 99, 100, 103, 104, 106, 111, and 113-115 are pending in the present application in which claims 61 and 90 are in independent form. Applicant’s amendment to claims 67, 69, 94, 97, and 99 had obviated the claim objections indicated in the previous office action.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 61-63, 67, 73, 76, 81, 83-85, 89, 90-92, 94, 95, 97, 99, 100, 103, 104, 106, 111, and 113-115 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-34 of U.S. Patent No. 11,424,177. Although the claims at issue are not identical, they are not patentably distinct from each other because claim of the instant application are encompassed by the claimed invention of U.S. Patent No. 11,424,177, see comparison table below.
Claims of instant application
Claims of U.S. Patent No. 11,424,177
61. A semiconductor device, comprising: a semiconductor die that comprises at least one secondary device area; a support; and a die attach material comprising at least one channel, at least a portion of the at least one channel positioned between the at least one secondary device area of the semiconductor die and the support to allow gases generated during attachment of the semiconductor die to the support to be released from the die attach material.
1. A package, comprising, a semiconductor die comprising at least one active area and at least one secondary device area; a support configured to support the semiconductor die; a die attach material; the semiconductor die being mounted on the support using the die attach material; and the die attach material including at least one channel, wherein the at least one channel is configured to allow gases generated during curing of the die attach material to be released from the die attach material; and wherein the at least one channel is located vertically below and laterally offset from the at least one active area.
2. The package according to claim 1 wherein the at least one channel is arranged under the at least one secondary device area.
62. The semiconductor device according to claim 61 wherein: the semiconductor die is a Group III nitride based HEMT (high-electron-mobility transistor).
12. The package according to claim 1 wherein: the at least one active area is an area that one or more Radio Frequency (RF) semiconductor devices are located; the one or more Radio Frequency (RF) semiconductor devices include at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the at least one secondary device area comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks.
63. The semiconductor device according to claim 61 wherein: the semiconductor die is a Group III-nitride based MMIC (monolithic microwave integrated circuit).
10. The package according to claim 1 wherein: the package comprises at least one of the following: a power amplifier package, a microwave power package, a microwave power amplifier package, a Radio Frequency (RF) amplifier package, a Radio Frequency (RF) power amplifier package, a Radio Frequency (RF) power transistor package, a monolithic microwave integrated circuit (MMIC) package, and a Radio Frequency (RF) power amplifier transistor package; and the semiconductor die comprises a monolithic integrated circuit.
67. The semiconductor device according to claim 61 wherein: the at least one channel comprises at least two channels that intersect at an intersection to form a mesh of channels.
5. The package according to claim 1 wherein: the at least one channel dissects the die attach material; and a first implementation of the at least one channel intersects with a second implementation of the at least one channel.
73. The semiconductor device according to claim 61 wherein: the at least one channel is located vertically below and laterally offset from an active area of the semiconductor die; the semiconductor die comprises an integrated circuit; and the at least one channel is arranged directly under the at least one secondary device area.
1. A package, comprising, a semiconductor die comprising at least one active area and at least one secondary device area; a support configured to support the semiconductor die; a die attach material; the semiconductor die being mounted on the support using the die attach material; and the die attach material including at least one channel, wherein the at least one channel is configured to allow gases generated during curing of the die attach material to be released from the die attach material; and wherein the at least one channel is located vertically below and laterally offset from the at least one active area.
76. The semiconductor device according to claim 61 wherein the at least one channel comprises at least one of the following: a rectangular shape, a polygonal shape, a circular shape, a freeform shape, a continuous shape, a discontinuous shape, and combinations thereof, and wherein the at least one channel includes at least one exhaust opening.
4. The package according to claim 1 wherein the at least one channel comprises at least one of the following: a rectangular shape, a polygonal shape, a circular shape, a freeform shape, a discontinuous shape, and combinations thereof.
81. The semiconductor device according to claim 61 wherein the die attach material is configured utilizing screen-printing processes with a stencil having openings consistent with formations of the die attach material and the stencil having portions not allowing application of the die attach material consistent with locations of the at least one channel; and wherein the stencil forms the at least one channel in the die attach material.
8. The package according to claim 1 wherein the die attach material is configured to be applied utilizing one of the following: screen-printing processes, preform processes, needle dispensing processes, and inkjet dispensing processes.
83. The semiconductor device according to claim 61 wherein the semiconductor die comprises at least one active area that comprises at least one of the following: an area that one or more transistors are located, an area that one or more transistor amplifiers are located, an area that one or more transformers are located, an area that one or more voltage regulators are located, an area that one or more devices that generate heat are located, an area that one or more devices that benefit from lower temperature operation are located, and an area that one or more semiconductor devices are located; and wherein gases generated during curing of the die attach material propagate into the at least one channe..
11. The package according to claim 1 wherein the at least one active area includes at least one of the following: an area that one or more transistors are located, an area that one or more transistor amplifiers are located, an area that one or more transformers are located, an area that one or more voltage regulators are located, an area that one or more devices that generate heat are located, an area that one or more devices that benefit from lower temperature operation are located, and an area that one or more semiconductor devices are located.
84. The semiconductor device according to claim 61 wherein: the semiconductor die comprises at least one active area that is an area that one or more Radio Frequency (RF) semiconductor devices are located; the semiconductor die comprises at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the at least one secondary device area comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks., wherein the at least one channel is arranged directly under the at least one secondary device area
12. The package according to claim 1 wherein: the at least one active area is an area that one or more Radio Frequency (RF) semiconductor devices are located; the one or more Radio Frequency (RF) semiconductor devices include at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the at least one secondary device area comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks.
85. The semiconductor device according to claim 61 wherein: the semiconductor die comprises at least one active area that is an area that one or more semiconductor devices are located; and the semiconductor die comprises at least one of the following: a wide band-gap semiconductor device, an ultra-wideband device, a GaN based device, a GaN-on-SiC device, a GaN-on-Si device, a Metal Semiconductor Field-Effect Transistor (MESFET), a Metal Oxide Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), a Bipolar Junction Transistor (BJT), laterally-diffused metal-oxide semiconductor (LDMOS), an Insulated Gate Bipolar Transistor (IGBT), a high-electron-mobility transistor (HEMT), and a Wide Band Gap (WBG) semiconductor, and the at least one channel is located vertically below and laterally offset from the at least one active area
13. The package according to claim 1 wherein: the at least one active area is an area that one or more semiconductor devices are located; and the one or more semiconductor devices include at least one of the following: a wide band-gap semiconductor device, an ultra-wideband device, a GaN based device, a GaN-on-SiC device, a GaN-on-Si device, a Metal Semiconductor Field-Effect Transistor (MESFET), a Metal Oxide Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), a Bipolar Junction Transistor (BJT), laterally-diffused metal-oxide semiconductor (LDMOS), an Insulated Gate Bipolar Transistor (IGBT), a high-electron mobility transistor (HEMT), and a Wide Band Gap (WBC) semiconductor.
89. The semiconductor device according to claim 61 further comprising an over-mold configuration that at least surrounds the semiconductor die, wherein the die attach material comprises at least a portion of at least one channel positioned between the over-mold configuration and the support; and wherein the over-mold configuration is attached at least in part to the die attach material.
17. The package according to claim 1 further comprising an over-mold configuration that at least surrounds the semiconductor die.
90. A semiconductor device, comprising: a semiconductor die; a support; and a die attach material comprising at least one channel; and an over-mold configuration that at least surrounds the semiconductor die and the over-mold configuration is attached at least in part to the die attach material.
1. A package, comprising, a semiconductor die comprising at least one active area and at least one secondary device area; a support configured to support the semiconductor die; a die attach material; the semiconductor die being mounted on the support using the die attach material; and the die attach material including at least one channel, wherein the at least one channel is configured to allow gases generated during curing of the die attach material to be released from the die attach material; and wherein the at least one channel is located vertically below and laterally offset from the at least one active area.
17. The package according to claim 1 further comprising an over-mold configuration that at least surrounds the semiconductor die.
91. The semiconductor device according to claim 90 wherein: the semiconductor die is a Group III nitride based HEMT (high-electron-mobility transistor).
12. The package according to claim 1 wherein: the at least one active area is an area that one or more Radio Frequency (RF) semiconductor devices are located; the one or more Radio Frequency (RF) semiconductor devices include at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the at least one secondary device area comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks.
92. The semiconductor device according to claim 90 wherein: the semiconductor die is a Group III-nitride based MMIC (monolithic microwave integrated circuit).
10. The package according to claim 1 wherein: the package comprises at least one of the following: a power amplifier package, a microwave power package, a microwave power amplifier package, a Radio Frequency (RF) amplifier package, a Radio Frequency (RF) power amplifier package, a Radio Frequency (RF) power transistor package, a monolithic microwave integrated circuit (MMIC) package, and a Radio Frequency (RF) power amplifier transistor package; and the semiconductor die comprises a monolithic integrated circuit.
94. The semiconductor device according to claim 90 further comprising at least one secondary device area on the support and wherein die attach material comprises at least a portion of the at least one channel positioned between the at least one secondary device area and the support and wherein the at least one channel is arranged directly under the at least one secondary device area.
1. A package, comprising, a semiconductor die comprising at least one active area and at least one secondary device area; a support configured to support the semiconductor die; a die attach material; the semiconductor die being mounted on the support using the die attach material; and the die attach material including at least one channel, wherein the at least one channel is configured to allow gases generated during curing of the die attach material to be released from the die attach material; and wherein the at least one channel is located vertically below and laterally offset from the at least one active area.
2. The package according to claim 1 wherein the at least one channel is arranged under the at least one secondary device area.
95. The semiconductor device according to claim 90 further comprising a protective material on the support and wherein the die attach material comprises at least a portion of at least one channel positioned between the protective material and the support.
17. The package according to claim 1 further comprising an over-mold configuration that at least surrounds the semiconductor die. Note that part of the over-mold that contacting the die attach material can act as the protective material.
97. The semiconductor device according to claim 90 wherein: the at least on channel comprises at least two channels that intersect at an intersection to form a mesh of channels.
5. The package according to claim 1 wherein: the at least one channel dissects the die attach material; and a first implementation of the at least one channel intersects with a second implementation of the at least one channel.
99. The semiconductor device according to claim 90 wherein: the at least one channel forms a mesh comprising multiple intersecting channels.
5. The package according to claim 1 wherein: the at least one channel dissects the die attach material; and a first implementation of the at least one channel intersects with a second implementation of the at least one channel.
100. The semiconductor device according to claim 90 wherein: the die attach material comprises metal particles in an organic material.
16. The package according to claim 1 wherein the die attach material includes one or more metal materials and one or more non-metal materials.
103. The semiconductor device according to claim 90 wherein: the at least one channel is located vertically below and laterally offset from an active area of the semiconductor die; the semiconductor die comprises an integrated circuit; and the at least one channel is arranged directly under at least one secondary device area of the semiconductor die.
10. The package according to claim 1 wherein: the package comprises at least one of the following: a power amplifier package, a microwave power package, a microwave power amplifier package, a Radio Frequency (RF) amplifier package, a Radio Frequency (RF) power amplifier package, a Radio Frequency (RF) power transistor package, a monolithic microwave integrated circuit (MMIC) package, and a Radio Frequency (RF) power amplifier transistor package; and the semiconductor die comprises a monolithic integrated circuit.
104. The semiconductor device according to claim 90 wherein: the at least one channel is arranged under at least one secondary device area; and the semiconductor die comprises a monolithic microwave integrated circuit (MMIC); and the at least one channel is located vertically below and laterally offset from an active area of the semiconductor die.
10. The package according to claim 1 wherein: the package comprises at least one of the following: a power amplifier package, a microwave power package, a microwave power amplifier package, a Radio Frequency (RF) amplifier package, a Radio Frequency (RF) power amplifier package, a Radio Frequency (RF) power transistor package, a monolithic microwave integrated circuit (MMIC) package, and a Radio Frequency (RF) power amplifier transistor package; and the semiconductor die comprises a monolithic integrated circuit.
106. The semiconductor device according to claim 90 wherein the at least one channel comprises at least one of the following: a rectangular shape, a polygonal shape, a circular shape, a freeform shape, a continuous shape, a discontinuous shape, and combinations thereof, and includes at least one exhaust opening.
4. The package according to claim 1 wherein the at least one channel comprises at least one of the following: a rectangular shape, a polygonal shape, a circular shape, a freeform shape, a discontinuous shape, and combinations thereof.
111. The semiconductor device according to claim 90 wherein the die attach material is configured utilizing screen-printing processes with a stencil having openings consistent with formations of the die attach material and the stencil having portions not allowing application of the die attach material consistent with locations of the at least one channel.
9. The package according to claim 1 wherein the die attach material is applied utilizing screen-printing processes with a stencil having openings consistent with formations of the die attach material and the stencil having portions not allowing application of the die attach material consistent with locations of the at least one channel.
113. The semiconductor device according to claim 90 wherein the semiconductor die comprises at least one active area that comprises at least one of the following: an area that one or more transistors are located, an area that one or more transistor amplifiers are located, an area that one or more transformers are located, an area that one or more voltage regulators are located, an area that one or more devices that generate heat are located, an area that one or more devices that benefit from lower temperature operation are located, and an area that one or more semiconductor devices are located; and wherein gases generated during curing of the die attach material propagate into the at least one chanel.
11. The package according to claim 1 wherein the at least one active area includes at least one of the following: an area that one or more transistors are located, an area that one or more transistor amplifiers are located, an area that one or more transformers are located, an area that one or more voltage regulators are located, an area that one or more devices that generate heat are located, an area that one or more devices that benefit from lower temperature operation are located, and an area that one or more semiconductor devices are located.
114. The semiconductor device according to claim 90 wherein: the semiconductor die comprises at least one active area that is an area that one or more Radio Frequency (RF) semiconductor devices are located; the semiconductor die comprises at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the semiconductor die comprises at least one secondary device area that comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks; and the at least one channel is arranged directly under the at least one secondary device area.
12. The package according to claim 1 wherein: the at least one active area is an area that one or more Radio Frequency (RF) semiconductor devices are located; the one or more Radio Frequency (RF) semiconductor devices include at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the at least one secondary device area comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks.
115. The semiconductor device according to claim 90 wherein: the semiconductor die comprises at least one active area that is an area that one or more semiconductor devices are located; and the semiconductor die comprises at least one of the following: a wide band-gap semiconductor device, an ultra-wideband device, a GaN based device, a GaN-on-SiC device, a GaN-on-Si device, a Metal Semiconductor Field-Effect Transistor (MESFET), a Metal Oxide Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), a Bipolar Junction Transistor (BJT), laterally-diffused metal-oxide semiconductor (LDMOS), an Insulated Gate Bipolar Transistor (IGBT), a high-electron-mobility transistor (HEMT), and a Wide Band Gap (WBG) semiconductor.
13. The package according to claim 1 wherein: the at least one active area is an area that one or more semiconductor devices are located; and the one or more semiconductor devices include at least one of the following: a wide band-gap semiconductor device, an ultra-wideband device, a GaN based device, a GaN-on-SiC device, a GaN-on-Si device, a Metal Semiconductor Field-Effect Transistor (MESFET), a Metal Oxide Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), a Bipolar Junction Transistor (BJT), laterally-diffused metal-oxide semiconductor (LDMOS), an Insulated Gate Bipolar Transistor (IGBT), a high-electron mobility transistor (HEMT), and a Wide Band Gap (WBC) semiconductor.
Claims 61-63, 65, 67, 69, 70, 73, 76, 81 and 83-85 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-22 of U.S. Patent No. 11,830,810. Although the claims at issue are not identical, they are not patentably distinct from each other because claim of the instant application are encompassed by the claimed invention of U.S. Patent No. 11,830,810, see comparison table below.
Claims of instant application
Claims of U.S. Patent No. 11,830,810
61. A semiconductor device, comprising: a semiconductor die that comprises at least one secondary device area; a support; and a die attach material comprising at least one channel, at least a portion of the at least one channel positioned between the at least one secondary device area of the semiconductor die and the support to allow gases generated during attachment of the semiconductor die to the support to be released from the die attach material.
1. A semiconductor device, comprising: a semiconductor die; a support; and a die attach material configured to attach a lower surface of the semiconductor die to an upper surface of the support, wherein the die attach material is structured and arranged on the support to comprise at least one channel, wherein the semiconductor die is arranged on at least a portion of the at least one channel arranged on the support, wherein the at least one channel is configured to allow gases generated during curing of the die attach material during attachment of the semiconductor die to the support to be released from the die attach material, and wherein the die attach material is configured such that the at least one channel is located vertically below and laterally offset from an active area of the semiconductor die.
3. The semiconductor device according to claim 1 further comprising at least one secondary device area on the support and wherein: the die attach material comprises at least a portion of the at least one channel positioned between the at least one secondary device area and the support; and the die attach material being arranged on the support such that the at least one channel is defined by one or more side edges of the die attach material, the lower surface of the semiconductor die and the upper surface of the support.
62. The semiconductor device according to claim 61 wherein: the semiconductor die is a Group III nitride based HEMT (high-electron-mobility transistor).
11. The semiconductor device according to claim 1 wherein: the semiconductor die comprises at least one active area that is an area that one or more Radio Frequency (RF) semiconductor devices are located; the semiconductor die comprises at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the semiconductor die comprises at least one secondary device area that comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks.
63. The semiconductor device according to claim 61 wherein: the semiconductor die is a Group III-nitride based MMIC (monolithic microwave integrated circuit).
13. The process of implementing a semiconductor device according to claim 12 wherein: the semiconductor die is a Group III-nitride based MMIC (monolithic microwave integrated circuit); and the forming the die attach material comprises forming a plurality of portions of the die attach material arranged on the support and the plurality of portions comprising the at least one channel therebetween.
65. The semiconductor device according to claim 61 further comprising a protective material on the support and wherein the die attach material comprises at least a portion of at least one channel positioned between the protective material and the support.
4. The semiconductor device according to claim 1 further comprising a protective material on the support and wherein the die attach material comprises at least a portion of at least one channel positioned between the protective material and the support.
67. The semiconductor device according to claim 61 wherein: the at least one channel comprises at least two channels that intersect at an intersection to form a mesh of channels.
12 wherein: the die attach material is configured such that the at least one channel comprises multiple channels within the die attach material.
17. The process of implementing a semiconductor device according to claim 12 wherein: the die attach material is configured such that the at least one channel forms a mesh within the die attach material.
69. The semiconductor device according to claim 61 wherein: the at least one channel forms a mesh and comprises multiple channels that intersect.
12 wherein: the die attach material is configured such that the at least one channel forms a mesh within the die attach material.
70. The semiconductor device according to claim 61 wherein: the die attach material comprises metal particles in an organic material.
12 wherein: the die attach material comprises metal particles in an organic material.
73. The semiconductor device according to claim 61 wherein: the at least one channel is located vertically below and laterally offset from an active area of the semiconductor die; the semiconductor die comprises an integrated circuit; and the at least one channel is arranged directly under the at least one secondary device area.
1. A semiconductor device, comprising: …wherein the die attach material is configured such that the at least one channel is located vertically below and laterally offset from an active area of the semiconductor die.
2. The semiconductor device according to claim 1 wherein: the semiconductor die is a Group III-nitride based MMIC (monolithic microwave integrated circuit); and the die attach material being arranged on the support to comprise a plurality of portions of the die attach material arranged between the semiconductor die and the support and the plurality of portions comprising the at least one channel therebetween.
76. The semiconductor device according to claim 61 wherein the at least one channel comprises at least one of the following: a rectangular shape, a polygonal shape, a circular shape, a freeform shape, a continuous shape, a discontinuous shape, and combinations thereof; and wherein the at least one channel includes at least one exhaust opening.
9. The semiconductor device according to claim 1 wherein the die attach material is configured such that the at least one channel comprises at least one of the following: a rectangular shape within the die attach material, a polygonal shape within the die attach material, a circular shape within the die attach material, a freeform shape within the die attach material, a continuous shape within the die attach material, a discontinuous shape within the die attach material, and combinations thereof.
81. The semiconductor device according to claim 61 wherein the die attach material is configured utilizing screen-printing processes with a stencil having openings consistent with formations of the die attach material and the stencil having portions not allowing application of the die attach material consistent with locations of the at least one channel; and wherein the stencil forms the at least one channel in the die attach material.
10. The semiconductor device according to claim 1 wherein: the die attach material is configured utilizing one of the following: die attach material screen-printing processes, die attach material preform processes, die attach material needle dispensing processes, and inkjet die attach material dispensing processes; and the die attach material comprises a plurality of portions of the die attach material arranged between the support.
83. The semiconductor device according to claim 61 wherein the semiconductor die comprises at least one active area that comprises at least one of the following: an area that one or more transistors are located, an area that one or more transistor amplifiers are located, an area that one or more transformers are located, an area that one or more voltage regulators are located, an area that one or more devices that generate heat are located, an area that one or more devices that benefit from lower temperature operation are located, and an area that one or more semiconductor devices are located; and wherein gases generated during curing of the die attach material propagate into the at least one channel.
1. The semiconductor device according to claim 1 wherein: the semiconductor die comprises at least one active area that is an area that one or more Radio Frequency (RF) semiconductor devices are located; the semiconductor die comprises at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the semiconductor die comprises at least one secondary device area that comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks.
84. The semiconductor device according to claim 61 wherein: the semiconductor die comprises at least one active area that is an area that one or more Radio Frequency (RF) semiconductor devices are located; the semiconductor die comprises at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the at least one secondary device area comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks; wherein the at least one channel is arranged directly under the at least one secondary device area.
1. The semiconductor device according to claim 1 wherein: the semiconductor die comprises at least one active area that is an area that one or more Radio Frequency (RF) semiconductor devices are located; the semiconductor die comprises at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the semiconductor die comprises at least one secondary device area that comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks.
85. The semiconductor device according to claim 61 wherein: the semiconductor die comprises at least one active area that is an area that one or more semiconductor devices are located; and the semiconductor die comprises at least one of the following: a wide band-gap semiconductor device, an ultra-wideband device, a GaN based device, a GaN-on-SiC device, a GaN-on-Si device, a Metal Semiconductor Field-Effect Transistor (MESFET), a Metal Oxide Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), a Bipolar Junction Transistor (BJT), laterally-diffused metal-oxide semiconductor (LDMOS), an Insulated Gate Bipolar Transistor (IGBT), a high-electron-mobility transistor (HEMT), and a Wide Band Gap (WBG) semiconductor; and the at least one channel is located vertically below and laterally offset from the at least one active area
1. The semiconductor device according to claim 1 wherein: the semiconductor die comprises at least one active area that is an area that one or more Radio Frequency (RF) semiconductor devices are located; the semiconductor die comprises at least one of the following: a GaN based Field-Effect Transistor (FET) and a GaN based high-electron-mobility transistor (HEMT); and the semiconductor die comprises at least one secondary device area that comprises portions of one or more of the following: impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic terminations, harmonic termination circuits, and matching networks.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 61, 65, 67, 69, 73, 76, 83, 85, 89, 90, 94, 95, 97, 99, 103, 106, 113, and 115 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yokoyama et al. (U.S. Pub. 2018/0366383).
In re claim 61, Yokoyama discloses a semiconductor device 101, comprising: a semiconductor die 3 that comprises at least one secondary device area (perimeter area of the semiconductor die 3) (see paragraph [0032] and fig. 1); a support 7 (see paragraph [0035] and fig. 1); and a die attach material 11 comprising at least one channel 15 (dividing lines 15), at least a portion of the at least one channel 15 positioned between the at least one secondary device area of the semiconductor die 3 and the support 7 to allow gases generated during attachment of the semiconductor die 3 to the support 7 to be released from the die attach material 11 (see paragraphs [0039], [0060] and figs. 1-2 and 7, note that, Yokoyama discloses by utilizing the dividing lines 15 which constitute as the at least one channel as a bypass passage for the bonder evaporated by heating, the gas resulting from evaporation of the binder can be suppresses from remaining in joining material 11 which constitutes as the die attach material, thus the at least one channel 15 allow gases generated during the attachment of the semiconductor die to the support to be release from the die attach material 11).
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In re claim 65, as applied to claim 61 above, Yokoyama discloses wherein the semiconductor device further comprising a protective material 5 on the support 7 and wherein the die attach material 11 comprises at least a portion of at least one channel 15 positioned between the protective material 5 and the support 7 (see paragraph [0036] and fig. 1).
In re claim 67, as applied to claim 61 above, Yokoyama discloses wherein the at least on channel 15 comprises at least two channels that intersect at an intersection to form a mesh of channels 15 (see paragraph [0038] and figs. 1-2).
In re claim 69, as applied to claim 61 above, Yokoyama discloses wherein the at least one channel 15 forms a mesh and comprises multiple channels that intersect (see paragraph [0038] and fig. 2).
In re claim 73, as applied to claim 61 above, Yokoyama discloses wherein the at least one channel 15 is located vertically below and laterally offset from an active area of the semiconductor die 3; and the semiconductor die 3 comprises an integrated circuit (an IGBT) and the at least one channel 15 is arranged directly under the at least one secondary device area (see paragraph [0034], note that, the at least one channel 15 is located at perimeter area of the semiconductor die and laterally offset from the central active area of the semiconductor die).
In re claim 76, as applied to claim 61 above, Yokoyama discloses wherein the at least one channel 15 comprises at least one of the following: a rectangular shape, a polygonal shape, a circular shape, a freeform shape, a continuous shape, a discontinuous shape, and combinations thereof, and wherein the at least one channel 15 includes at least one exhaust opening (see paragraph [0038] and figs. 1-2).
In re claim 83, as applied to claim 61 above, Yokoyama discloses wherein the semiconductor die 3 comprises at least one active area that comprises at least one of the following: an area that one or more transistors (an IGBT) are located, an area that one or more transistor amplifiers are located, an area that one or more transformers are located, an area that one or more voltage regulators are located, an area that one or more devices that generate heat are located, an area that one or more devices that benefit from lower temperature operation are located, and an area that one or more semiconductor devices are located; and wherein gases generated during curing of the die attach material propagate into the at least one channel (see paragraph [0034] and figs. 1-2).
In re claim 85, as applied to claim 61 above, Yokoyama discloses wherein the semiconductor die 3 comprises at least one active area that is an area that one or more semiconductor devices are located; and the semiconductor die comprises at least one of the following: a wide band-gap semiconductor device, an ultra-wideband device, a GaN based device, a GaN-on-SiC device, a GaN-on-Si device, a Metal Semiconductor Field-Effect Transistor (MESFET), a Metal Oxide Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), a Bipolar Junction Transistor (BJT), laterally-diffused metal-oxide semiconductor (LDMOS), an Insulated Gate Bipolar Transistor (IGBT), a high-electron-mobility transistor (HEMT), and a Wide Band Gap (WBG) semiconductor, and the at least one channel is located vertically below and laterally offset from the at least one active area (see paragraph [0034] and figs. 1-2, note that, the semiconductor device is an IGBT).
In re claim 89, as applied to claim 61 above, Yokoyama discloses wherein the semiconductor device further comprising an over-mold configuration 21 that at least surrounds the semiconductor die 3, wherein the die attach material 11 comprises at least a portion of at least one channel 15 positioned between the over-mold configuration 21 and the support 7; and wherein the over-mold configuration 21 is attached at least in part to the die attach material 11 (see paragraph [0073] and fig. 7).
In re claim 90, Yokoyama discloses a semiconductor device, comprising: a semiconductor die 3 (see paragraph [0032] and figs. 1-2); a support 7 (see paragraph [0035] and figs. 1-2); and a die attach material 11 comprising at least one channel 15 (see paragraph [0038] and figs. 1-2); and an over-mold configuration 21 that at least surrounds the semiconductor die 3 and the over-mold configuration 21 is attached at least in part to the die attach material 11 (see paragraph [0073] and fig. 7).
In re claim 94, as applied to claim 90 above, Yokoyama discloses wherein the semiconductor device further comprising at least one secondary device area (perimeter area of the semiconductor die 3) on the support 7 and wherein die attach material 11 comprises at least a portion of the at least one channel 15 positioned between the at least one secondary device area and the support 7 and wherein the at least one channel is arranged directly under the at least one secondary device area (see paragraph [0038] and figs. 1-2).
In re claim 95, as applied to claim 90 above, Yokoyama discloses wherein the semiconductor device further comprising a protective material 5 on the support 7 and wherein the die attach material 11 comprises at least a portion of at least one channel 15 positioned between the protective material 5 and the support 7 (see paragraph [0036] and fig. 1).
In re claim 97, as applied to claim 90 above, Yokoyama discloses wherein the at least one channel 15 comprises at least two channels that intersect at an intersection that form a mesh of channels (see paragraph [0036] and fig. 2).
In re claim 99, as applied to claim 90 above, Yokoyama discloses wherein the at least one channel 15 forms a mesh comprising multiple intersecting channels (see paragraph [0036] and fig. 2).
In re claim 103, as applied to claim 90 above, Yokoyama discloses wherein the at least one channel 15 is located vertically below and laterally offset from an active area of the semiconductor die 3; and the semiconductor die 3 comprises an integrated circuit (an IGBT); and the at least one channel is arranged directly under at least one secondary device area of the semiconductor die 3 (see paragraph [0034], note that, the at least one channel 15 is located at perimeter area of the semiconductor die and laterally offset from the central active area of the semiconductor die).
In re claim 106, as applied to claim 90 above, Yokoyama discloses wherein the at least one channel 15 comprises at least one of the following: a rectangular shape, a polygonal shape, a circular shape, a freeform shape, a continuous shape, a discontinuous shape, and combinations thereof, and includes at least one exhaust opening (see paragraph [0038] and figs. 1-2).
In re claim 113, as applied to claim 90 above, Yokoyama discloses wherein the semiconductor die 3 comprises at least one active area that comprises at least one of the following: an area that one or more transistors (an IGBT) are located, an area that one or more transistor amplifiers are located, an area that one or more transformers are located, an area that one or more voltage regulators are located, an area that one or more devices that generate heat are located, an area that one or more devices that benefit from lower temperature operation are located, and an area that one or more semiconductor devices are located; and wherein gases generated during curing of the die attach material propagate into the at least one channel (see paragraph [0034] and figs. 1-2).
In re claim 115, as applied to claim 90 above, Yokoyama discloses wherein the semiconductor die 3 comprises at least one active area that is an area that one or more semiconductor devices are located; and the semiconductor die comprises at least one of the following: a wide band-gap semiconductor device, an ultra-wideband device, a GaN based device, a GaN-on-SiC device, a GaN-on-Si device, a Metal Semiconductor Field-Effect Transistor (MESFET), a Metal Oxide Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), a Bipolar Junction Transistor (BJT), laterally-diffused metal-oxide semiconductor (LDMOS), an Insulated Gate Bipolar Transistor (IGBT), a high-electron-mobility transistor (HEMT), and a Wide Band Gap (WBG) semiconductor (see paragraph [0034] and figs. 1-2, note that the semiconductor die 3 is an IGBT).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 62, 63, 91, 92, and 104 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama et al. (U.S. Pub. 2018/0366383) in view of Schmukler (U.S. Pub. 2017/0033749).
In re claims 62, 63, 91, 92, 104, as applied to claims 61 and 90 above, respectively, Yokoyama discloses wherein the at least one channel 15 is arranged under at least one secondary device area; and the at least one channel 15 located vertically below and laterally offset from an active areas of the semiconductor die (see paragraph [0038] and figs. 1-2) but is silent to wherein the semiconductor die is a Group III nitride based HEMT (high-electron-mobility transistor) and wherein the semiconductor die is/comprises a Group III-nitride based MMIC (monolithic microwave integrated circuit).
However, Schmukler discloses in a same field of endeavor, a semiconductor device, including, inter-alia, wherein the semiconductor die is a Group III nitride based HEMT (high-electron-mobility transistor) (see paragraph [0043]) and wherein the semiconductor die is/comprises a Group III-nitride based MMIC (monolithic microwave integrated circuit) (see paragraph [0058]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Schmukler into the semiconductor die of Yokoyama in order to enable wherein the semiconductor die is a Group III nitride based HEMT (high-electron-mobility transistor) and wherein the semiconductor die is/comprises a Group III-nitride based MMIC (monolithic microwave integrated circuit) in Yokoyama to be formed for the purpose of using a device for high power, large currents, that can support high voltages and/or operate at high frequencies for radio frequency/microwave applications (see paragraphs [0002], [0003] of Schmukler).
Claim(s) 70 and 100 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama et al. (U.S. Pub. 2018/0366383) in view of Kobayashi et al. (U.S. Pub. 2015/0041974).
In re claims 70 and 100, as applied to claims 61 and 90 above, respectively, Yokoyama discloses wherein the die attach material 11 comprises silver nanoparticles (see paragraph [0047]) but is silent to wherein the die attach material comprises metal particles in an organic material.
However, Kobayashi discloses in a same field of endeavor, a semiconductor device including, inter-alia, wherein the die attach material comprises metal particles in an organic material so that it is possible to obtain a bonding memory to bond components of a semiconductor device that is capable of relieving stress on the semiconductor device and also has electrical conductivity (see paragraph [0087]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Kobayashi into the semiconductor die of Yokoyama in order to enable wherein the die attach material comprises metal particles in an organic material in Yokoyama to be formed for the purpose of using a die attach material to bond components of a semiconductor device that is capable of relieving stress on the semiconductor device and also has electrical conductivity (see paragraph [0087] of Kobayashi).
Claim(s) 81 and 111 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama et al. (U.S. Pub. 2018/0366383) in view of Hussain et al. (U.S. Pub. 2019/0259685).
In re claims 81 and 111, as applied to claims 61 and 90 above, Yokoyama is silent to wherein the die attach material is configured utilizing screen-printing processes with a stencil having openings consistent with formations of the die attach material and the stencil having portions not allowing application of the die attach material consistent with locations of the at least one channel; and wherein the stencil forms the at least one channel in the die attach material.
However, Hussain discloses in a same field of endeavor, a semiconductor device, including, inter-alia, wherein the die attach material is configured utilizing screen-printing processes with a stencil having openings consistent with formations of the die attach material and the stencil having portions not allowing application of the die attach material consistent with locations of the at least one channel; and wherein the stencil forms the at least one channel in the die attach material (see paragraph [0019]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Hussain into the semiconductor die of Yokoyama in order to enable wherein the die attach material is configured utilizing screen-printing processes with a stencil having openings consistent with formations of the die attach material and the stencil having portions not allowing application of the die attach material consistent with locations of the at least one channel; and wherein the stencil forms the at least one channel in the die attach material in Yokoyama to be formed in order to better control the placement of the liquid material (see paragraph [0019] of Hussain).
Response to Applicant’s Amendment and Arguments
Applicant's arguments filed July 27th, 2026 have been fully considered but they are not persuasive.
With respect to the non-statutory double patenting rejection of claims 61-63, 67, 73, 76, 81, 83-85, 89, 90-92, 94, 95, 99, 100, 103, 104, 106, 111, and 113-115 over claims 1-34 of U.S. Patent No. 11,424,177 and the non-statutory double patenting rejection of claims 61-63, 65, 67, 70, 73, 76, 81, and 83-85 over claims 1-22 of U.S. Patent No. 11,830,810, Applicant states that “Nevertheless, in order to expedite prosecution in the current application, Applicant has provided herewith a terminal disclaimer with respect to the referenced patent”. However, the office has not received the terminal disclaimer.
With respect to independent claim 61, Applicant contends that Yokoyama does not teach or suggest a semiconductor die that comprises at least one secondary device area, a die attach material comprising at least one channel, and at least one portion of the at least one channel positioned between the at least one secondary device area of the semiconductor die and the support to allow gases generated during attachment of the semiconductor die to the support to be released from the die attach material.
However, it is respectfully submitted that Applicant’s above argument is not persuasive because similar to Applicant’s claimed invention as recited in independent claim 61, Yokoyama discloses a semiconductor device 101, including, inter-alia, a semiconductor die 3 that comprises at least one secondary device area (perimeter area of the semiconductor die 3) (see paragraph [0032] and fig. 1); a support 7 (see paragraph [0035] and fig. 1); and a die attach material 11 comprising at least one channel 15 (dividing lines 15), at least a portion of the at least one channel 15 positioned between the at least one secondary device area of the semiconductor die 3 and the support 7 to allow gases generated during attachment of the semiconductor die 3 to the support 7 to be released from the die attach material 11 (see paragraphs [0039], [0060] and figs. 1-2 and 7).
“[0039] A paste material is applied onto joining material 11, which is then sintered, for example, to thereby join insulated circuit board 1 and buffer plate 5. This paste material is applied by methods such as a commonly-known screen printing method or a dispenser applying method. Depending on the type, the amount and the like of the binder contained in the paste material, the thickness of joining material 11 and the width of dividing line 15 (the width in the direction along one main surface 1a of insulated circuit board 1) are changed. Thus, the size of joining material 11 after being sintered will be hereinafter described. The width in a plan view in the direction intersecting with the extending direction of each dividing line 15 is, for example, preferably equal to or greater than 10 μm and also preferably equal to or less than the thickness of joining material 11. The same applies to the case where dividing line 15 is formed not only in joining material 11 as the first joining material shown in FIG. 2 but also in joining material 11 as the second joining material, for example, as will be described later.”
“[0060] Thus, in the present embodiment, joining material 11 for joining insulated circuit board 1 and buffer plate 5 to each other is divided into a plurality of portions, for example, in a mesh shape. This can improve the efficiency of causing the binder contained in joining material 11 during heat joining to be discharged through dividing line 15 used for dividing joining material 11 to the outside of joining material 11. Even the binder in the center portion of joining material 11 can be discharged to the outside through dividing line 15. In other words, by utilizing dividing line 15 as a bypass passage for the binder evaporated by heating, the gas resulting from evaporation of the binder can be suppressed from remaining in joining material 11. Thus, as redundant gas does not remain in joining material 11, joining material 11 is to be accordingly densely packed. Therefore, the joining strength of joining material 11 can be increased, and the reliability of joining material 11 can be improved. The joining strength of joining material 11 is increased, so that the heat dissipation performance from semiconductor element 3 to insulated circuit board 1 can be further improved.”
Thus, in view of the above, Yokoyama discloses by utilizing the dividing lines 15 which constitute as the at least one channel as a bypass passage for the bonder evaporated by heating, the gas resulting from evaporation of the binder can be suppresses from remaining in joining material 11 which constitutes as the die attach material, thus the at least one channel 15 allow gases generated during the attachment of the semiconductor die to the support to be release from the die attach material 11.
Further, notes that the claims are given the broadest reasonable interpretation (In re Hyatt, 211 F. 3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000)). It is respectfully submitted that Applicant’s claimed invention as recited in independent claim 61 does not defined a secondary device area that is differentiate from a perimeter regions or edges of the semiconductor die in Yokoyama and that the claimed invention only requires that the die attach material to be in the position between the at least one secondary device area of the semiconductor die and the support. Therefore, Yokoyama discloses that the channels 15 of the die attach material 11 are positioned between the perimeter region or edges of the semiconductor die 3 and the support 7 (see marked-up version of fig. 7 below).
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Applicant further states that “The present specification explains that the at least one secondary device may be defined as a passive area and may implement RF circuitry, including resistors, inductors, capacitors, impedance matching circuits, matching networks, harmonic terminations, couplers, baluns, power combiners, RF circuits, radial stub circuits, transmission line circuits, integrated passive devices, and related structures”.
However, in response to Applicant's above argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the at least one secondary device may be defined as a passive area and may implement RF circuitry, including resistors, inductors, capacitors, impedance matching circuits, matching networks, harmonic terminations, couplers, baluns, power combiners, RF circuits, radial stub circuits, transmission line circuits, integrated passive devices, and related structures”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
With respect to independent claim 90, Applicant contends that Yokoyama does not disclose an over-mold configuration surrounding the semiconductor die and attached at least in part to the die attach material.
However, it is respectfully submitted that Applicant’s above argument is not persuasive because Yokoyama discloses similar to Applicant’s claimed invention as recited in independent claim 90, a semiconductor device, including, inter-alia, a semiconductor die 3 (see paragraph [0032] and figs. 1-2); a support 7 (see paragraph [0035] and figs. 1-2); and a die attach material 11 comprising at least one channel 15 (see paragraph [0038] and figs. 1-2); and an over-mold configuration 21 that at least surrounds the semiconductor die 3 and the over-mold configuration 21 is attached at least in part to the die attach material 11 (see paragraph [0073] and fig. 7).
“[0073] First, the configuration of a power module in the present embodiment will be hereinafter described with reference to FIG. 6. Referring to FIG. 6, since a power module 401 in the present embodiment has basically the same configuration as that of power module 101 in the first embodiment, the same components are designated by the same reference characters, and description thereof will not be repeated. Note that power module 401 in the present embodiment is different from power module 101 in the first embodiment in that a resin material 21 is disposed so as to cover a joining material end face 11e corresponding to an end face of joining material 11 serving as the first joining material. Also, power module 401 in FIG. 6 is configured as in the third embodiment that a plurality of semiconductor elements 3 are disposed on buffer plate 5 to be spaced apart from each other. However, power module 401 may also be configured as in power module 101 in the first embodiment such that only a single semiconductor element 3 is provided.”
Thus, Yokoyama discloses in paragraph [0073] and fig. 7, that a resin material 21 which constitutes as an over-mold configuration that is covered the sidewalls of the die attach material 11 and being attached at least in part to the die attach material 11 (see marked-up version of fig. 7 below).
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For this reason, it is respectfully submitted that the rejection is proper.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
