Prosecution Insights
Last updated: July 17, 2026
Application No. 18/505,496

SYSTEMS AND METHODS FOR BOND TREATING AND CLEAVING OF SILICON WAFERS

Non-Final OA §102§103
Filed
Nov 09, 2023
Examiner
MENZ, DOUGLAS M
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Globalwafers Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
686 granted / 776 resolved
+20.4% vs TC avg
Minimal +5% lift
Without
With
+4.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
32 currently pending
Career history
807
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
52.1%
+12.1% vs TC avg
§102
36.2%
-3.8% vs TC avg
§112
0.6%
-39.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 776 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, claims 1-13, in the reply filed on 4/24/26 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 9-10 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Henley et al. (US 6153524). Regarding claim 1, Henley discloses a semiconductor wafer processing system for processing a set of semiconductor wafers (Abstract, figs. 1-3 and Col. 2), the system comprising: a bond treat station including an oven (26, figs. 1-3 and Cols. 4-5); a cleave station including a cleave assembly for cleaving the wafer (22, figs. 1-3 and Cols. 4-5); a transfer robot (20, fig. 1 and Col. 4); and a controller for controlling the transfer robot (Col. 5), wherein the controller is programmed to: control the transfer robot to retrieve a first wafer of the set of semiconductor wafers from the bond treat station (Cols. 5-7); and control the transfer robot to deliver the first wafer to the cleave station for processing by the cleave assembly (Cols. 5-7). Regarding claim 2, Henley further discloses a machine frame, wherein the bond treat station, the cleave station, and the transfer robot are each at least partially positioned within the machine frame (figs. 1-2). Regarding claim 9, Henley further discloses a load port (28, figs. 1-3 and Col. 4), wherein the first wafer is a bonded pair wafer, and wherein the controller is further programmed to: control the cleave assembly to cleave the first wafer to separate a handle wafer of the bonded pair from a donor wafer (Cols. 5-7); and control the transfer robot to deliver the handle wafer to a wafer pod at the load port (Cols. 5-7). Regarding claim 10, Henley further discloses wherein the cleave assembly includes a mechanical cleave tool (Col. 15). Regarding claim 12, Henley further discloses wherein the controller is programmed to: control the transfer robot to deliver each wafer from the set of wafers to the cleave station; and control the cleave assembly to cleave each wafer of the set of wafers within a predefined maximum dwell time (Cols. 5-7). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Henley et al. (US 6153524). Regarding claim 13, Henley discloses the semiconductor wafer processing system of claim 12, as mentioned above. Henley does not explicitly disclose wherein the predefined maximum dwell time is less than four hours. However, such dwell time is within the parameters of established semiconductor manufacturing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing. Allowable Subject Matter Claims 3-8 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 3, there is no teaching or suggestion in the art of record disclosing the semiconductor wafer processing system of claim 1, wherein the bond treat station further includes a queueing robot for holding a first cassette, wherein the transfer robot retrieves the first wafer from the first cassette at the bond treat station. Claims 4-8 depend on claim 3. Regarding claim 11, there is no teaching or suggestion in the art of record disclosing the semiconductor wafer processing system of claim 1 in combination with the limitations of claim 11, wherein the controller is further programmed to control a queueing robot to load the wafer cassette into the oven at the bond treat station, wherein the controller controls the transfer robot to retrieve the first wafer from the bond treat station after the first wafer is processed in the oven. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 20040107014 discloses a relevant apparatus for processing wafers. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 5/30/26
Read full office action

Prosecution Timeline

Nov 09, 2023
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+4.6%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 776 resolved cases by this examiner. Grant probability derived from career allowance rate.

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