Attorney’s Docket Number: 0756-12690
Filing Date: 11/09/2023
Continuity Data: RCE filed on 10/07/2025
Claimed Priority Date: 01/19/2021 (CON of 17/151,941 now PAT 11,817,508)
02/26/2018 (DIV of 15/904,867 now PAT 10,985,283)
03/13/2017 (JP 2017-047019)
03/03/2017 (JP 2017-041019)
Applicants: Koezuka et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Request for Continued Examination (RCE) filed on 10/07/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
Applicant's amendment filed on 10/07/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claims 1 and 4-14, and added new claim 15. Accordingly, pending in this application are claims 2-3 and 15.
Response to Amendment
Applicant’s amendments to the Claims filed on 10/07/2025 have overcome the claim rejections under 35 U.S.C. 103, as previously formulated in the Final Office action mailed on 07/09/2025. However, new grounds of rejection are presented below, as necessitated by Applicant’s amendments to the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2-3 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okazaki et al. (US20215/0171116).
Regarding Claim 2, Okazaki (see, e.g., Figs. 1A-C, 2, and 10) shows all aspects of the instant invention, including a semiconductor device (e.g., transistor 150) comprising:
- a first conductive layer (e.g., conductive film 104) in contact with a top surface of a substrate (e.g., substrate 102), the first conductive layer comprising a region configured to function as a gate electrode of a transistor (see, e.g., Par. [0061]: 104 functioning as a gate electrode)
- a first insulating layer (e.g., insulating film 106a) comprising a region over and in contact with a top surface of the first conductive layer, the first insulating layer comprising a region configured to function as a gate insulating layer of the transistor (see, e.g., Par. [0063]: insulating film 106 is a two-layer structure 106a,106b functioning as a gate insulating film)
- a second insulating layer (e.g., insulating film 106b) comprising a region over and in contact with a top surface of the first insulating layer, the second insulating layer comprising a region configured to function as a gate insulating layer of the transistor
- a metal oxide layer (see, e.g., Par. [0064],[0071]: oxide semiconductor layer 108 can be a In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf)) comprising a region over and in contact with a top surface of the second insulating layer
- a third insulating layer (e.g., insulating film 110) comprising a region over and in contact with a top surface of the metal oxide layer
- a second conductive layer (e.g., electrode 112a) comprising a region over and in contact with the top surface of the metal oxide layer in a first opening (e.g., opening 140a) provided in the third insulating layer and a region in contact with a top surface of the third insulating layer, the second conductive layer being configured to function as one of a source electrode and a drain electrode of the transistor (see, e.g., Par. [0111]: electrodes 112a and 112b functioning as a source electrode and a drain electrode)
- a third conductive layer (e.g., electrode 112b) comprising a region over and in contact with the top surface of the metal oxide layer in a second opening (e.g., opening 140b) provided in the third insulating layer and a region in contact with the top surface of the third insulating layer, the third conductive layer being configured to function as the other of the source electrode and the drain electrode of the transistor
- a fourth insulating layer (e.g., insulating film 114) comprising a region over and in contact with the top surface of the third insulating layer, a region over and in contact with a top surface of the second conductive layer, and a region over and in contact with a top surface of the third conductive layer
- a fifth insulating layer (e.g., insulating film 118) comprising a region over the fourth insulating layer
- wherein the metal oxide layer comprises a channel formation region of the transistor (see, e.g., Par. [0064]: 108 comprises a channel region)
- wherein the first conductive layer comprises copper and titanium (see, e.g., Par. [0082]: 104 can be an alloy of, e.g., Cu and Ti)
- wherein the first insulating layer comprises silicon and nitrogen (see, e.g., Par. [0088]: 106a is a silicon nitride film)
- wherein the second insulating layer comprises a region with a higher oxygen concentration than the first insulating layer (see, e.g., Par. [0086],[0088]: 106b is a silicon oxide film containing oxygen in excess of the stoichiometric composition)
- wherein the second conductive layer (e.g., 112a) comprises a first titanium film and a first copper film comprising a region in contact with a top surface of the first titanium film (see, e.g., Par. [0113]: electrodes 112a and 112b have a two-layer structure in which a copper film is stacked on a titanium film)
- wherein the third conductive layer (e.g., 112b) comprises a second titanium film and a second copper film comprising a region in contact with a top surface of the second titanium film
- wherein the fourth insulating layer comprises silicon and oxygen (see, e.g., Par. [0115]: 114 can be a silicon oxide film or a silicon oxynitride film)
- wherein the fifth insulating layer comprises silicon and nitrogen (see, e.g., Par. [0125]: 118 can be a silicon nitride or a silicon nitride oxide)
Regarding Claim 3, Okazaki (see, e.g., Figs. 1A-C, 2, and 10) shows all aspects of the instant invention, including a semiconductor device (e.g., transistor 150) comprising:
- a first conductive layer (e.g., conductive film 104) over in contact with a top surface of a substrate (e.g., substrate 102), the first conductive layer comprising a region configured to function as a gate electrode of a transistor (see, e.g., Par. [0061]: 104 functioning as a gate electrode)
- a first insulating layer (e.g., insulating film 106a) comprising a region over and in contact with a top surface of the first conductive layer, the first insulating layer comprising a region configured to function as a gate insulating layer of the transistor (see, e.g., Par. [0063]: insulating film 106 is a two-layer structure 106a,106b functioning as a gate insulating film)
- a second insulating layer (e.g., insulating film 106b) comprising a region over and in contact with a top surface of the first insulating layer, the second insulating layer comprising a region configured to function as a gate insulating layer of the transistor
- a metal oxide layer (see, e.g., Par. [0064],[0071]: oxide semiconductor layer 108 can be a In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf)) comprising a region over and in contact with a top surface of the second insulating layer
- a third insulating layer (e.g., insulating film 110) comprising a region over and in contact with a top surface of the metal oxide layer
- a second conductive layer (e.g., electrode 112a) comprising a region over and in contact with the top surface of the metal oxide layer in a first opening (e.g., opening 140a) provided in the third insulating layer and a region in contact with a top surface of the third insulating layer, the second conductive layer being configured to function as one of a source electrode and a drain electrode of the transistor (see, e.g., Par. [0111]: electrodes 112a and 112b functioning as a source electrode and a drain electrode)
- a third conductive layer (e.g., electrode 112b) comprising a region over and in contact with the top surface of the metal oxide layer in a second opening (e.g., opening 140b) provided in the third insulating layer and a region in contact with the top surface of the third insulating layer, the third conductive layer being configured to function as the other of the source electrode and the drain electrode of the transistor
- a fourth insulating layer (e.g., insulating film 114) comprising a region over and in contact with the top surface of the third insulating layer, a region over and in contact with a top surface of the second conductive layer, and a region over and in contact with a top surface of the third conductive layer
- a fifth insulating layer (e.g., insulating film 118) comprising a region over the fourth insulating layer
- a fourth conductive layer (e.g., conductive film 120a) comprising a region over and in contact with the top surface of the second conductive layer or the top surface of the third conductive layer in a third opening (e.g., opening 142c) provided in the fourth insulating layer and the fifth insulating layer, the fourth conductive layer being configured to function as a pixel electrode (see, e.g., Par. [0064]: 120a functions as a pixel electrode used for a display device)
- wherein the metal oxide layer comprises a channel formation region of the transistor (see, e.g., Par. [0064]: 108 comprises a channel region)
- wherein the first conductive layer comprises copper and titanium (see, e.g., Par. [0082]: 104 can be an alloy of, e.g., Cu and Ti)
- wherein the first insulating layer comprises silicon and nitrogen (see, e.g., Par. [0088]: 106a is a silicon nitride film)
- wherein the second insulating layer comprises a region with a higher oxygen concentration than the first insulating layer (see, e.g., Par. [0086],[0088]: 106b is a silicon oxide film containing oxygen in excess of the stoichiometric composition)
- wherein the second conductive layer (e.g., 112a) comprises a first titanium film and a first copper film comprising a region in contact with a top surface of the first titanium film (see, e.g., Par. [0113]: electrodes 112a and 112b have a two-layer structure in which a copper film is stacked on a titanium film)
- wherein the third conductive layer (e.g., 112b) comprises a second titanium film and a second copper film comprising a region in contact with a top surface of the second titanium film
- wherein the fourth insulating layer comprises silicon and oxygen (see, e.g., Par. [0115]: 114 can be a silicon oxide film or a silicon oxynitride film)
- wherein the fifth insulating layer comprises silicon and nitrogen (see, e.g., Par. [0125]: 118 can be a silicon nitride or a silicon nitride oxide)
Regarding Claim 15, Okazaki (see, e.g., Figs. 1A-C, 2, and 10) shows all aspects of the instant invention, including a semiconductor device (e.g., transistor 150) comprising:
- a first conductive layer (e.g., conductive film 104) over in contact with a top surface of a substrate (e.g., substrate 102), the first conductive layer comprising a region configured to function as a gate electrode of a transistor (see, e.g., Par. [0061]: 104 functioning as a gate electrode)
- a first insulating layer (e.g., insulating film 106a) comprising a region over and in contact with a top surface of the first conductive layer, the first insulating layer comprising a region configured to function as a gate insulating layer of the transistor (see, e.g., Par. [0063]: insulating film 106 is a two-layer structure 106a,106b functioning as a gate insulating film)
- a second insulating layer (e.g., insulating film 106b) comprising a region over and in contact with a top surface of the first insulating layer, the second insulating layer comprising a region configured to function as a gate insulating layer of the transistor
- a metal oxide layer (see, e.g., Par. [0064],[0071]: oxide semiconductor layer 108 can be a In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf)) comprising a region over and in contact with a top surface of the second insulating layer
- a third insulating layer (e.g., insulating film 110) comprising a region over and in contact with a top surface of the metal oxide layer
- a second conductive layer (e.g., electrode 112a) comprising a region over and in contact with the top surface of the metal oxide layer in a first opening (e.g., opening 140a) provided in the third insulating layer and a region in contact with a top surface of the third insulating layer, the second conductive layer being configured to function as one of a source electrode and a drain electrode of the transistor (see, e.g., Par. [0111]: electrodes 112a and 112b functioning as a source electrode and a drain electrode)
- a third conductive layer (e.g., electrode 112b) comprising a region over and in contact with the top surface of the metal oxide layer in a second opening (e.g., opening 140b) provided in the third insulating layer and a region in contact with the top surface of the third insulating layer, the third conductive layer being configured to function as the other of the source electrode and the drain electrode of the transistor
- a fourth insulating layer (e.g., insulating film 114) comprising a region over and in contact with the top surface of the third insulating layer, a region over and in contact with a top surface of the second conductive layer, and a region over and in contact with a top surface of the third conductive layer
- a fifth insulating layer (e.g., insulating film 118) comprising a region over the fourth insulating layer
- a fourth conductive layer (e.g., conductive film 120a) comprising a region over and in contact with the top surface of the second conductive layer or the top surface of the third conductive layer in a third opening (e.g., opening 142c) provided in the fourth insulating layer and the fifth insulating layer, the fourth conductive layer being configured to function as a pixel electrode (see, e.g., Par. [0064]: 120a functions as a pixel electrode used for a display device)
- wherein the metal oxide layer comprises a channel formation region of the transistor (see, e.g., Par. [0064]: 108 comprises a channel region)
- wherein the metal oxide comprises indium, gallium, and zinc (see, e.g., Par. [0071]: 108 comprises In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf))
- wherein the first conductive layer comprises copper and titanium (see, e.g., Par. [0082]: 104 can be an alloy of, e.g., Cu and Ti)
- wherein the first insulating layer comprises silicon and nitrogen (see, e.g., Par. [0088]: 106a is a silicon nitride film)
- wherein the second insulating layer comprises a region with a higher oxygen concentration than the first insulating layer (see, e.g., Par. [0086],[0088]: 106b is a silicon oxide film containing oxygen in excess of the stoichiometric composition)
- wherein the second conductive layer (e.g., 112a) comprises a first titanium film and a first copper film comprising a region in contact with a top surface of the first titanium film (see, e.g., Par. [0113]: electrodes 112a and 112b have a two-layer structure in which a copper film is stacked on a titanium film)
- wherein the third conductive layer (e.g., 112b) comprises a second titanium film and a second copper film comprising a region in contact with a top surface of the second titanium film
- wherein the fourth insulating layer comprises silicon and oxygen (see, e.g., Par. [0115]: 114 can be a silicon oxide film or a silicon oxynitride film)
- wherein the fifth insulating layer comprises silicon and nitrogen (see, e.g., Par. [0125]: 118 can be a silicon nitride or a silicon nitride oxide)
Conclusion
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814