CTNF 18/505,631 CTNF 87644 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25 AIA Applicant's election with traverse of Species A (Fig. 2-15; Claims 1-4 and 6-20) in the reply filed on 04/16/2026 is acknowledged. The traversal is on the ground(s) that election of species as being improperly characterized . This is not found persuasive because The Examiner notes there is a search and/or examination burden for the patentably distinct species as set forth above because at least the following reason(s) apply: the species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search queries), the prior art applicable to one species would not likely be applicable to the other species. Since absent Applicant admission on record that species (as characterized by the Applicant or the Examiner) are obvious variants of each other . The requirement is still deemed proper and is therefore made FINAL. Claim 5 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species B, there being no allowable generic or linking claim. Claim 8, 10, 11 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species B (Fig. 16-24 “the performing the process includes removing a portion of a metal gate layer” “removing a metal layer adjacent the second one of the plurality of vertically stacked channel layers”) there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 04/16/2026. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-02 AIA Claim s 2, 14 and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claims 2, 14 and 19 recite “wherein R, R1, R2, R3 are each an alkyl series”. The Examiner notes that written description is not enabled for every single alkyl series . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-4, 6, 7, 9, 12-14, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. (US 10,256,158 B1) in view of Fang et al. (US 2016/0190240 A1) . Regarding Claim 1, Frougier (Fig. 1-72) discloses a method, comprising: providing a first set of channel nanostructures (114).and a second set of channel nanostructures stacked (118) in a vertical direction above a semiconductor substrate (102); providing an opening (“recesses through the multi-layer structure extending into the substrate 102”) over the semiconductor substrate (102); using deposition to deposit a dummy material (104) in the opening adjacent one of the first set or the second set of channel nanostructures (114, 118); performing a process (“conformally forming additional amounts of the liner dielectric 110”, Fig. 15, 16)) while the dummy material (104) is in the opening (See 104 on the lower portion of the opening); after performing the process, removing the dummy material (“the isolation insulator 104 exposed, a material removal process (e.g., oxide isotropic recess (BHS)) is performed to remove the isolation insulator 104”) (Fig. 17); and forming a first gate (150 surrounded 114) surrounding the first set of channel nanostructures (114) and a second gate (150 surrounding 118) surrounding the second set of channel nanostructures (118). Frougier does not explicitly disclose using spin-on deposition to deposit a dummy material. [0025] Fang (Fig. 5-8) discloses spin-on deposition to deposit a dummy material (140). [0025] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method in Frougier in view of Fang by using spin-on deposition to deposit a dummy material in order to improve quality of dummy material [0025-0026] Regarding Claim 2, Frougier in view of Fang discloses the method of claim 1, wherein the dummy material is one of SiOC or SiOx.(SiOx) Regarding Claim 3, Frougier in view of Fang discloses method of claim 1, Frougier in view of Fang does not explicitly disclose wherein the depositing the dummy material includes introducing at least one compound of the following compounds: PNG media_image1.png 104 584 media_image1.png Greyscale and wherein R, R1, R2, R3 are each an alkyl series and each of n, l and m are greater than 0. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method in Frougier in view of Fang such that the dummy material includes introducing at least one compound of the following compounds: PNG media_image1.png 104 584 media_image1.png Greyscale and wherein R, R1, R2, R3 are each an alkyl series and each of n, l and m are greater than 0 since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp. , 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07). Regarding Claim 4, Frougier in view of Fang discloses the method of claim 1, wherein the providing the opening includes etching the opening in a source/drain region (146). Regarding Claim 6, Frougier in view of Fang discloses the method of claim 1, further comprising: prior to performing the process, etching back the dummy material. (Fig. 14) Regarding Claim 7, Frougier in view of Fang discloses the method of claim 1, wherein the performing the process includes depositing a liner layer (liner dielectric 110) on sidewalls of the opening. (Fig. 15) Regarding Claim 9, Frougier (Fig. 1-72) discloses a method comprising: receiving a substrate (102) having a plurality of vertically stacked channel layers (114, 118); forming a first transistor of a first type (nFET) having a channel region in a first one of the plurality of vertically stacked channel layers (114) and forming a second transistor of a second type (pFET) having a channel region in a second one of the plurality of vertically stacked channel layers (118); using deposition to deposit a dummy material (104) laterally adjacent the first one of the plurality of vertically stacked channel layers (114) and laterally adjacent the second one of the plurality of vertically stacked channel layers (118); and etching back the deposited dummy material (104) to provide a top surface of the dummy material (104) below the second one of the plurality of vertically stacked channel layers (118) (Fig. 14); and performing a process directed to the second transistor. (pFET). Frougier does not explicitly disclose using spin-on deposition to deposit a dummy material. Fang (Fig. 5-8) discloses spin-on deposition to deposit a dummy material (140). [0025] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method in Frougier in view of Fang by using spin-on deposition to deposit a dummy material in order to improve quality of dummy material [0025-0026] Regarding Claim 12, Frougier in view of Fang discloses the method of claim 9, wherein the process includes etching depositing a dielectric liner layer (liner dielectric 110) on the second one of the plurality of vertically stacked channel layers (118) (Fig. 14, 15). Regarding Claim 13, Frougier in view of Fang discloses the method of claim 12, wherein the dielectric liner layer (liner dielectric 110) is disposed directly on the dummy material (104). (Fig. 14, 15). Regarding Claim 14, Frougier in view of Fang discloses the method of claim 9, Frougier in view of Fang does not explicitly disclose wherein the spin-on deposition includes depositing least one compound from a group of compounds consisting of: PNG media_image1.png 104 584 media_image1.png Greyscale and wherein R, R1, R2, R3 are each an alkyl series and each of n, l and m are greater than 0. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method in Frougier in view of Fang such that the spin-on deposition includes depositing least one compound from a group of compounds consisting of: PNG media_image1.png 104 584 media_image1.png Greyscale and wherein R, R1, R2, R3 are each an alkyl series and each of n, l and m are greater than 0 since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp. , 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07). Regarding Claim 18, Frougier discloses the method of claim 15, wherein Frougier does not explicitly disclose the depositing the dummy material includes spin-on deposition process. Fang (Fig. 5-8) discloses spin-on deposition to deposit a dummy material (140). [0025] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method in Frougier in view of Fang by using spin-on deposition to deposit a dummy material in order to improve quality of dummy material [0025-0026] Regarding Claim 19, Frougier in view of Fang discloses the method of claim 18. Frougier in view of Fang does not explicitly disclose wherein the spin-on deposition includes depositing least one compound from a group of compounds consisting of: PNG media_image1.png 104 584 media_image1.png Greyscale and wherein R, R1, R2, R3 are each an alkyl series and each of n, l and m are greater than 0. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method in Frougier in view of Fang such that the spin-on deposition includes depositing least one compound from a group of compounds consisting of: PNG media_image1.png 104 584 media_image1.png Greyscale and wherein R, R1, R2, R3 are each an alkyl series and each of n, l and m are greater than 0 since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp. , 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07) . 07-21-aia AIA Claim (s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. (US 10,256,158 B1) . Regarding Claim 20, Frougier discloses the method of claim 15, wherein Frougier does not explicitly disclose the etching back the dummy material includes a planarization process followed by a plasma etching process. However, Frougier discloses planarized top surface of the dummy material (104, Fig. 13) followed by a plasma etching process (“dry pulsing etch-deposition”) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method in Frougier by using a planarization process followed by a plasma etching process in order to isolation insulator is recessed down to a level above the lower semiconductor layer [column 6, lines 19-40, Frougier] Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 15-17 is/are rejected under 35 U.S.C. 102 (A1) as being anticipated by Frougier et al. (US 10,256,158 B1) . Regarding Claim 15, Frougier (Fig. 1-72) discloses a method, comprising: forming a trench (“recesses through the multi-layer structure extending into the substrate 102”) in a source drain region (source/drain regions)of a transistor stack (“nFET and pFET epitaxial source/drain regions”), the trench extending through a source/drain region of an upper transistor (nFET) and a lower transistor (pFET); depositing a dummy material filling (104) the trench; etching back the dummy material (104) to form an opening in the trench in the source/drain region of the upper transistor (nFET) and the etched back dummy material disposed in the source/drain region of the lower transistor (pFET); (Fig. 14-15) depositing a dielectric liner (liner dielectric 110) on sidewalls of the opening in the source/drain region of the upper transistor (nFET) (Fig. 15); removing the etched back dummy material (Fig. 17); and forming a first epitaxial region (146) associated with the lower transistor (pFET) while the dielectric liner (110) is on the sidewalls of the opening in the source/drain region of the upper transistor. (nFET) (Fig. 17) Regarding Claim 16, Frougier discloses the method of claim 15, further comprising: removing the dielectric liner (110); forming an isolation layer (144) on the first epitaxial region (146) in the trench; and forming a second epitaxial region (142) associated with the upper transistor (pFET) over the isolation layer (144). Regarding Claim 17, Frougier discloses the method of claim 16, further comprising: forming a metal gate structure (150, 152) for each of the lower transistor (nFET) and the upper transistor (pFET). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent- center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DMITRIY YEMELYANOV/Examiner, Art Unit 2891 Application/Control Number: 18/505,631 Page 2 Art Unit: 2891 Application/Control Number: 18/505,631 Page 3 Art Unit: 2891 Application/Control Number: 18/505,631 Page 4 Art Unit: 2891 Application/Control Number: 18/505,631 Page 5 Art Unit: 2891 Application/Control Number: 18/505,631 Page 6 Art Unit: 2891 Application/Control Number: 18/505,631 Page 7 Art Unit: 2891 Application/Control Number: 18/505,631 Page 8 Art Unit: 2891 Application/Control Number: 18/505,631 Page 9 Art Unit: 2891 Application/Control Number: 18/505,631 Page 10 Art Unit: 2891 Application/Control Number: 18/505,631 Page 11 Art Unit: 2891 Application/Control Number: 18/505,631 Page 12 Art Unit: 2891 Application/Control Number: 18/505,631 Page 13 Art Unit: 2891
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