DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Applicant's election without traverse of claims 1-16 in the reply filed on 1/15/2026 is acknowledged.
3. Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group.
4. Applicant cancelled claims 17-20; and added claims 21-24.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7, 9, 10, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2024/0420959) (hereafter Xie).
Regarding claim 1, Xie discloses a method for isolating a metal gate, the method comprising:
forming a gate line 136 (Fig. 4, paragraph 0059) over a semiconductor substrate 102 (Fig. 4, paragraph 0058);
patterning a mask 138 (Fig. 7, paragraph 0081) over the gate line 136 (Fig. 7), wherein an opening 161 (Fig. 7, paragraph 0081) in the mask 138 (Fig. 7) is located over a region (see a region of 136 is removed in Fig. 8) of the gate line 136 (Fig. 8) to be removed;
performing an etching process 170 (Fig. 8, paragraph 0098) through the opening 161 (Fig. 7) to form a trench 173 (Fig. 8); and
forming an isolation feature 180 (Fig. 10, paragraph 0106) in the trench 173 (Fig. 10), wherein the isolation feature 180 (Fig. 10) is selectively formed with no air gap, with a small air gap 181 (Fig. 10, paragraph 0106), or with a full air gap.
Regarding claim 2, Xie further discloses the method of claim 1, wherein the gate line 136 (Fig. 4, paragraph 0059, wherein “sacrificial gate 136”) is a dummy gate line, and wherein the method further comprises: after forming the isolation feature 180 (Fig. 10, paragraph 0106) in the trench 173 (Fig. 10), removing (see Fig. 11 and paragraph 0113) the dummy gate line 136 (Fig. 10) to form a gate cavity; and forming a metal gate structure 194 (Fig. 11, paragraph 0117) in the gate cavity and adjacent to the isolation feature 180 (Fig. 11).
Regarding claim 3, Xie further discloses the method of claim 1, wherein the gate line is a metal gate line 194 (Fig. 11, paragraph 0119), and wherein the method further comprises: forming a dummy gate line 136 (Fig. 4, paragraph 0059) over the semiconductor substrate 102 (Fig. 4, paragraph 0058); forming an interlayer dielectric 152 (Fig. 4, paragraph 0119) adjacent to the dummy gate line 136 (Fig. 4); and removing (see Fig. 11, paragraph 0114) the dummy gate line 136 (Fig. 4) to form a gate cavity; wherein forming the gate line 194 (Fig. 11, paragraph 0113) over the semiconductor substrate 102 (Fig. 11) comprises forming the metal gate line 194 (Fig. 11) in the gate cavity.
Regarding claim 7, Xie further discloses the method of claim 1, wherein: forming the isolation feature 180 (Fig. 10, paragraph 0106) in the trench comprises depositing a single layer 180 (Fig. 10; and see paragraph 0021, wherein “dielectric material”) of isolation material.
Regarding claim 9, Xie further discloses the method of claim 1, wherein forming the isolation feature 180 (Fig. 10) in the trench 173 (Fig. 10) comprises performing a deposition process to deposit isolation material 180 (Fig. 10, paragraph 0106) in the trench, and wherein the method further comprises controlling the etching process 170 (Fig. 8, paragraph 0088) and the deposition process (see Fig. 10 and paragraph 0105) to form a selected air gap 181 (Fig. 10) at a desired depth within the isolation feature 180 (Fig. 10).
Regarding claim 10, Xie discloses a method comprising:
designing a layout of an integrated circuit 100 (Fig. 11, paragraph 0050) including a device 100 (Fig. 11) comprising a first gate structure 194.sub.1 (Fig. 11, paragraph 0120) and a second gate structure 194.sub.2 (Fig. 11, paragraph 0120) separated by an isolation feature 180 (Fig. 11, paragraph 0120);
determining a desired device performance condition (see paragraph 0120, wherein “Reduction of such parasitic capacitance(s) may improve performance of the semiconductor IC device 100 and may allow for further semiconductor IC device scaling.”) and/or a desired process yield condition;
selecting a structure of the isolation feature 180 (Fig. 11, paragraph 0120) to provide the desired device performance condition (see paragraph 0120, wherein “The air pocket 181 may reduce the parasitic capacitance between adjacent gate structures. For example, the air pocket 181 within the gate cut region 180 instances that separate adjacent replacement gate structure(s) 194.sub.1, 194.sub.2, and 194.sub.3 may relatively reduce the parasitic capacitance between the replacement gate structure(s) 194.sub.1, 194.sub.2, and 194.sub.3 compared to a gate cut dielectric instances with no air pocket”), wherein the structure of the isolation feature 180 (Fig. 11; and see paragraph 0109, wherein “Different instances of air pocket 181 can have relative differences in shape, size, location, or the like, because of manufacturing tolerance effects and/or to independently improve or optimize parasitic capacitance decreases between adjacent gate structures.”) comprises a selected shape; and
performing an integrated circuit fabrication process comprising:
forming a gate line 136 (Fig. 4, paragraph 0059) over a semiconductor substrate 102 (Fig. 4, paragraph 0058);
performing an etching process 170 (Fig. 8, paragraph 0098) to remove a portion of the gate line 136 (Fig. 8) and form a trench 173 (Fig. 8) with the selected shape; and
forming an isolation feature (180 and 181 in Fig. 10, paragraph 0106) in the trench, wherein the isolation feature (180 and 181 in Fig. 10) is selectively formed with no air gap, with a small air gap 181 (Fig. 10, paragraph 0106), or with a full air gap.
Regarding claim 16, Xie further discloses the method of claim 10, wherein: the structure of the isolation feature (180 and 181 in Fig. 10) comprises a selected depth of an air gap 181 (Fig. 10, paragraph 0105) within the isolation feature (180 and 181 in Fig. 10); and forming the isolation feature (180 and 181 in Fig. 10) in the trench 173 (Fig. 10) comprises forming the isolation feature (180 and 181 in Fig. 10) with a small air gap 181 (Fig. 10) or with a full air gap at the selected depth.
Claims 1, 4, 8, 10, 11, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2019/0067277) (hereafter Tsai).
Regarding claim 1, Tsai discloses a method for isolating a metal gate, the method comprising:
forming a gate line 110 (Fig. 8, paragraph 0012) over a semiconductor substrate 102 (Fig. 8, paragraph 0012);
patterning a mask 170 (Fig. 9, paragraph 0035) over the gate line 110 (Fig. 9), wherein an opening 113 (Fig. 9, paragraph 0035) in the mask 170 (Fig. 9) is located over a region of the gate line 110 (Fig. 10) to be removed;
performing an etching process (see Fig. 10, paragraph 0036) through the opening 113 (Fig. 9) to form a trench 113 (Fig. 10); and
forming an isolation feature 114 (Fig. 11, paragraph 0013) in the trench 113 (Fig. 10), wherein the isolation feature 114 (Fig. 11) is selectively formed with no air gap (see Fig. 11), with a small air gap, or with a full air gap.
Regarding claim 4, Tsai further discloses the method of claim 1, wherein performing the etching process (see Fig. 10, paragraph 0036) through the opening 113 (Fig. 9) to form the trench 113 (Fig. 10) comprises forming a V-shaped trench 113 (Fig. 10); and forming the isolation feature 114 (Fig. 11, paragraph 0013) in the trench 113 (Fig. 10) comprises forming the isolation feature 114 (Fig. 11) with no air gap (see Fig. 11 and paragraph 0011).
Regarding claim 8, Tsai (utilize different elements for an isolation feature as applied in claim 1 in the above) discloses a method for isolating a metal gate, the method comprising:
forming a gate line 110 (Fig. 8, paragraph 0012) over a semiconductor substrate 102 (Fig. 8, paragraph 0012);
patterning a mask 170 (Fig. 9, paragraph 0035) over the gate line 110 (Fig. 9), wherein an opening 113 (Fig. 9, paragraph 0035) in the mask 170 (Fig. 9) is located over a region of the gate line 110 (Fig. 10) to be removed;
performing an etching process (see Fig. 10, paragraph 0036) through the opening 113 (Fig. 9) to form a trench 113 (Fig. 10); and
forming an isolation feature (114 and 116 in Fig. 1B, paragraph 0021) in the trench 113 (Fig. 10), wherein the isolation feature (114 and 116 in Fig. 1B) is selectively formed with no air gap (see Fig. 1B), with a small air gap, or with a full air gap; and
wherein: forming the isolation feature (114 and 116 in Fig. 1B; see claim filed on 1/15/2026 did not disclose forming entire of the isolation feature in the trench such that a portion 114 (Fig. 1B) of the isolation feature (114 and 116 in Fig. 1B) can be formed in the trench 113 (Fig. 10)) in the trench 113 (Fig. 10) comprises depositing multiple layer (114 and 116 in Fig. 1B, paragraph 0021) of isolation material to form a multi-layer isolation feature.
Regarding claim 10, Tsai discloses a method comprising:
designing a layout of an integrated circuit 100 (Fig. 1B, paragraph 0012) including a device 100 (Fig. 11) comprising a first gate structure (left 112 in Fig. 1B, paragraph 0012) and a second gate structure (right 112 in Fig. 1B, paragraph 0012) separated by an isolation feature 114 (Fig. 1B, paragraph 0013);
determining a desired device performance condition (paragraph 0011, wherein “A cut metal gate process refers to a fabrication process where after a metal gate (e.g., a high-k metal gate or HK MG) replaces a dummy gate structure (e.g., a polysilicon gate), the metal gate is cut (e.g., by an etching process) to separate the metal gate into two or more portions. Each portion functions as a metal gate for an individual transistor.”) and/or a desired process yield condition;
selecting a structure of the isolation feature 114 (Fig. 1B) to provide the desired device performance condition (see paragraph 0011, wherein “the CMG trench so produced has slanted sidewalls. Such tapered profile helps the filling of the isolation material into the CMG trench to eliminate gap or voids in the isolation material”), wherein the structure of the isolation feature 114 (Fig. 1B) comprises a selected shape (“slanted sidewalls” in paragraph 0011); and
performing an integrated circuit fabrication process comprising:
forming a gate line 110 (Fig. 8, paragraph 0012) over a semiconductor substrate 102 (Fig. 8, paragraph 0012);
performing an etching process (see Fig. 10, paragraph 0036) to remove a portion of the gate line 110 (Fig. 9) and form a trench 113 (Fig. 10) with the selected shape; and
forming an isolation feature 114 (Fig. 11, paragraph 0013) in the trench 113 (Fig. 10), wherein the isolation feature 114 (Fig. 11) is selectively formed with no air gap (see Fig. 11 and paragraph 0011), with a small air gap, or with a full air gap.
Regarding claim 11, Tsai further discloses the method of claim 10, wherein: the selected shape is a V-shape 113 (Fig. 10); and forming the isolation feature 114 (Fig. 11, paragraph 0013) in the trench 113 (Fig. 10) comprises forming the isolation feature 114 (Fig. 11) with no air gap (see Fig. 11 and paragraph 0011).
Regarding claim 15, Tsai (utilize different elements for an isolation feature as applied in claim 10 in the above) discloses a method comprising:
designing a layout of an integrated circuit 100 (Fig. 1B, paragraph 0012) including a device 100 (Fig. 11) comprising a first gate structure (left 112 in Fig. 1B, paragraph 0012) and a second gate structure (right 112 in Fig. 1B, paragraph 0012) separated by an isolation feature 114 (Fig. 1B, paragraph 0013);
determining a desired device performance condition (paragraph 0011, wherein “A cut metal gate process refers to a fabrication process where after a metal gate (e.g., a high-k metal gate or HK MG) replaces a dummy gate structure (e.g., a polysilicon gate), the metal gate is cut (e.g., by an etching process) to separate the metal gate into two or more portions. Each portion functions as a metal gate for an individual transistor.”) and/or a desired process yield condition;
selecting a structure of the isolation feature 114 (Fig. 1B) to provide the desired device performance condition (see paragraph 0011, wherein “the CMG trench so produced has slanted sidewalls. Such tapered profile helps the filling of the isolation material into the CMG trench to eliminate gap or voids in the isolation material”), wherein the structure of the isolation feature 114 (Fig. 1B) comprises a selected shape (“slanted sidewalls” in paragraph 0011); and
performing an integrated circuit fabrication process comprising:
forming a gate line 110 (Fig. 8, paragraph 0012) over a semiconductor substrate 102 (Fig. 8, paragraph 0012);
performing an etching process (see Fig. 10, paragraph 0036) to remove a portion of the gate line 110 (Fig. 9) and form a trench 113 (Fig. 10) with the selected shape; and
forming an isolation feature (114 and 116 in Fig. 1B, paragraph 0021) in the trench 113 (Fig. 10), wherein the isolation feature (114 and 116 in Fig. 1B) is selectively formed with no air gap (see Fig. 1B), with a small air gap, or with a full air gap; and
wherein: forming the isolation feature (114 and 116 in Fig. 1B; see claim filed on 1/15/2026 did not disclose forming entire of the isolation feature in the trench such that a portion 114 (Fig. 1B) of the isolation feature (114 and 116 in Fig. 1B) can be formed in the trench 113 (Fig. 10)) in the trench 113 (Fig. 10) comprises depositing multiple layer (114 and 116 in Fig. 1B, paragraph 0021) of isolation material or materials to form a multi-layer isolation feature (114 and 116 in Fig. 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 2019/0067277) (hereafter Tsai).
Regarding claim 5, Tsai (utilize different elements for an isolation feature as applied in claim 1 in the above) discloses a method for isolating a metal gate, the method comprising:
forming a gate line 110 (Fig. 8, paragraph 0012) over a semiconductor substrate 102 (Fig. 8, paragraph 0012);
patterning a mask 170 (Fig. 9, paragraph 0035) over the gate line 110 (Fig. 9), wherein an opening 113 (Fig. 9, paragraph 0035) in the mask 170 (Fig. 9) is located over a region of the gate line 110 (Fig. 10) to be removed;
performing an etching process (see Fig. 10, paragraph 0036) through the opening 113 (Fig. 9) to form a trench 113 (Fig. 10); and
forming an isolation feature 113 (Fig. 10) in the trench 113 (Fig. 10), wherein the isolation feature 113 (Fig. 10) is selectively formed with no air gap, with a small air gap (see Fig. 10), or with a full air gap; and
wherein: performing the etching process (see Fig. 10, paragraph 0036) through the opening 113 (Fig. 9) to form the trench 113 (Fig. 10); and forming the isolation feature 113 (Fig. 10) in the trench 113 (Fig. 10) comprises forming the isolation feature 113 (Fig. 10) with a small air gap 113 (Fig. 10).
Tsai did not explicitly disclose performing the etching process through the opening to form the trench comprises forming a spear-shaped trench.
Regarding the limitation, “performing the etching process through the opening to form the trench comprises forming a spear-shaped trench”, the claim filed on 1/15/2026 did not define “a spear-shaped trench”. In addition, Tsai discloses performing the etching process (see Fig. 10, paragraph 0036) through the opening 113 (Fig. 9) to form the trench 113 (Fig. 10) comprises forming the trench 113 (Fig. 10, paragraph 0022) having a tapered profile. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tsai to include performing the etching process through the opening to form the trench comprises forming a spear-shaped trench, since such a modification would have involved a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed invention was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 6, Tsai (utilize different elements for an isolation feature as applied in claim 1 in the above) discloses a method for isolating a metal gate, the method comprising:
forming a gate line 110 (Fig. 8, paragraph 0012) over a semiconductor substrate 102 (Fig. 8, paragraph 0012);
patterning a mask 170 (Fig. 9, paragraph 0035) over the gate line 110 (Fig. 9), wherein an opening 113 (Fig. 9, paragraph 0035) in the mask 170 (Fig. 9) is located over a region of the gate line 110 (Fig. 10) to be removed;
performing an etching process (see Fig. 10, paragraph 0036) through the opening 113 (Fig. 9) to form a trench 113 (Fig. 10); and
forming an isolation feature 113 (Fig. 10) in the trench 113 (Fig. 10), wherein the isolation feature 113 (Fig. 10) is selectively formed with no air gap, with a small air gap, or with a full air gap (see Fig. 10); and
wherein: performing the etching process (see Fig. 10, paragraph 0036) through the opening 113 (Fig. 9) to form the trench 113 (Fig. 10); and forming the isolation feature 113 (Fig. 10) in the trench 113 (Fig. 10) comprises forming the isolation feature 113 (Fig. 10) with a full air gap 113 (Fig. 10).
Tsai did not explicitly disclose performing the etching process through the opening to form the trench comprises forming a carrot-shaped trench.
Regarding the limitation, “performing the etching process through the opening to form the trench comprises forming a carrot-shaped trench”, the claim filed on 1/15/2026 did not define “a carrot-shaped trench”. In addition, Tsai discloses performing the etching process (see Fig. 10, paragraph 0036) through the opening 113 (Fig. 9) to form the trench 113 (Fig. 10) comprises forming the trench 113 (Fig. 10, paragraph 0022) having a tapered profile. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tsai to include performing the etching process through the opening to form the trench comprises forming a carrot-shaped trench, since such a modification would have involved a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed invention was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 12, Tsai (utilize different elements for an isolation feature as applied in claim 10 in the above) discloses a method comprising:
designing a layout of an integrated circuit 100 (Fig. 1B, paragraph 0012) including a device 100 (Fig. 11) comprising a first gate structure (left 112 in Fig. 1B, paragraph 0012) and a second gate structure (right 112 in Fig. 1B, paragraph 0012) separated by an isolation feature 114 (Fig. 1B, paragraph 0013);
determining a desired device performance condition (paragraph 0011, wherein “A cut metal gate process refers to a fabrication process where after a metal gate (e.g., a high-k metal gate or HK MG) replaces a dummy gate structure (e.g., a polysilicon gate), the metal gate is cut (e.g., by an etching process) to separate the metal gate into two or more portions. Each portion functions as a metal gate for an individual transistor.”) and/or a desired process yield condition;
selecting a structure of the isolation feature 114 (Fig. 1B) to provide the desired device performance condition (see paragraph 0011, wherein “the CMG trench so produced has slanted sidewalls. Such tapered profile helps the filling of the isolation material into the CMG trench to eliminate gap or voids in the isolation material”), wherein the structure of the isolation feature 114 (Fig. 1B) comprises a selected shape (“slanted sidewalls” in paragraph 0011); and
performing an integrated circuit fabrication process comprising:
forming a gate line 110 (Fig. 8, paragraph 0012) over a semiconductor substrate 102 (Fig. 8, paragraph 0012);
performing an etching process (see Fig. 10, paragraph 0036) to remove a portion of the gate line 110 (Fig. 9) and form a trench 113 (Fig. 10) with the selected shape;
forming an isolation feature 113 (Fig. 10, paragraph 0021) in the trench 113 (Fig. 10), wherein the isolation feature 113 (Fig. 10) is selectively formed with no air gap, with a small air gap 113 (Fig. 10), or with a full air gap; and
forming the isolation feature 113 (Fig. 10) in the trench 113 (Fig. 10) comprises forming the isolation feature 113 (Fig. 10) with a small air gap 113 (Fig. 10).
Tsai did not explicitly disclose the selected shape is a spear-shape.
Regarding the limitation, “the selected shape is a spear-shape”, the claim filed on 1/15/2026 did not define “a spear-shape”. In addition, Tsai discloses the selected shape 113 (Fig. 9) having a tapered profile. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tsai to include the selected shape is a spear-shape, since such a modification would have involved a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed invention was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 13, Tsai (utilize different elements for an isolation feature as applied in claim 10 in the above) discloses a method comprising:
designing a layout of an integrated circuit 100 (Fig. 1B, paragraph 0012) including a device 100 (Fig. 11) comprising a first gate structure (left 112 in Fig. 1B, paragraph 0012) and a second gate structure (right 112 in Fig. 1B, paragraph 0012) separated by an isolation feature 114 (Fig. 1B, paragraph 0013);
determining a desired device performance condition (paragraph 0011, wherein “A cut metal gate process refers to a fabrication process where after a metal gate (e.g., a high-k metal gate or HK MG) replaces a dummy gate structure (e.g., a polysilicon gate), the metal gate is cut (e.g., by an etching process) to separate the metal gate into two or more portions. Each portion functions as a metal gate for an individual transistor.”) and/or a desired process yield condition;
selecting a structure of the isolation feature 114 (Fig. 1B) to provide the desired device performance condition (see paragraph 0011, wherein “the CMG trench so produced has slanted sidewalls. Such tapered profile helps the filling of the isolation material into the CMG trench to eliminate gap or voids in the isolation material”), wherein the structure of the isolation feature 114 (Fig. 1B) comprises a selected shape (“slanted sidewalls” in paragraph 0011); and
performing an integrated circuit fabrication process comprising:
forming a gate line 110 (Fig. 8, paragraph 0012) over a semiconductor substrate 102 (Fig. 8, paragraph 0012);
performing an etching process (see Fig. 10, paragraph 0036) to remove a portion of the gate line 110 (Fig. 9) and form a trench 113 (Fig. 10) with the selected shape;
forming an isolation feature 113 (Fig. 10, paragraph 0021) in the trench 113 (Fig. 10), wherein the isolation feature 113 (Fig. 10) is selectively formed with no air gap, with a small air gap 113 (Fig. 10), or with a full air gap; and
forming the isolation feature 113 (Fig. 10) in the trench 113 (Fig. 10) comprises forming the isolation feature 113 (Fig. 10) with a full air gap 113 (Fig. 10).
Tsai did not explicitly disclose the selected shape is a spear-shape.
Regarding the limitation, “the selected shape is a carrot-shape”, the claim filed on 1/15/2026 did not define “a carrot-shape”. In addition, Tsai discloses the selected shape 113 (Fig. 9) having a tapered profile. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tsai to include the selected shape being a carrot-shape, since such a modification would have involved a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed invention was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 14, Tsai (utilize different elements for an isolation feature as applied in claim 10 in the above) discloses a method comprising:
designing a layout of an integrated circuit 100 (Fig. 1B, paragraph 0012) including a device 100 (Fig. 11) comprising a first gate structure (left 112 in Fig. 1B, paragraph 0012) and a second gate structure (right 112 in Fig. 1B, paragraph 0012) separated by an isolation feature 114 (Fig. 1B, paragraph 0013);
determining a desired device performance condition (paragraph 0011, wherein “A cut metal gate process refers to a fabrication process where after a metal gate (e.g., a high-k metal gate or HK MG) replaces a dummy gate structure (e.g., a polysilicon gate), the metal gate is cut (e.g., by an etching process) to separate the metal gate into two or more portions. Each portion functions as a metal gate for an individual transistor.”) and/or a desired process yield condition;
selecting a structure of the isolation feature 114 (Fig. 1B) to provide the desired device performance condition (see paragraph 0011, wherein “the CMG trench so produced has slanted sidewalls. Such tapered profile helps the filling of the isolation material into the CMG trench to eliminate gap or voids in the isolation material”), wherein the structure of the isolation feature 114 (Fig. 1B) comprises a selected shape (“slanted sidewalls” in paragraph 0011); and
performing an integrated circuit fabrication process comprising:
forming a gate line 110 (Fig. 8, paragraph 0012) over a semiconductor substrate 102 (Fig. 8, paragraph 0012);
performing an etching process (see Fig. 10, paragraph 0036) to remove a portion of the gate line 110 (Fig. 9) and form a trench 113 (Fig. 10) with the selected shape;
forming an isolation feature 113 (Fig. 10, paragraph 0021) in the trench 113 (Fig. 10), wherein the isolation feature 113 (Fig. 10) is selectively formed with no air gap, with a small air gap 113 (Fig. 10), or with a full air gap; and
forming the isolation feature 113 (Fig. 10) in the trench 113 (Fig. 10) comprises forming the isolation feature 113 (Fig. 10) with a full air gap 113 (Fig. 10).
Tsai did not explicitly disclose the selected shape is a spear-shape.
Regarding the limitation, “the selected shape is a carrot-shape”, the claim filed on 1/15/2026 did not define “a carrot-shape”. In addition, Tsai discloses the selected shape 113 (Fig. 9) having a tapered profile. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tsai to include the selected shape being a carrot-shape, since such a modification would have involved a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed invention was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2024/0420959) (hereafter Xie), in view of Tsai et al. (US 2019/0067277) (hereafter Tsai).
Regarding claim 21, Xie discloses a method of fabricating a gate-all-around semiconductor device, the method comprising:
forming a multi-layer structure (106 and 108 in Fig. 2, paragraph 0052) over a semiconductor substrate 102 (Fig. 2, paragraph 0058), the multi-layer structure (106 and 108 in Fig. 2) comprising alternating first semiconductor layers 106 (Fig. 2, paragraph 0052) and second semiconductor layers 108 (Fig. 2, paragraph 0052);
forming a fin structure 121 (Fig. 2, paragraph 0056) in the multi-layer structure (106 and 108 in Fig. 4);
forming a dummy gate electrode 136 (Fig. 4, paragraph 0059) over the fin structure 121 (Fig. 2);
removing (see Fig. 11 and paragraph 0114) the dummy gate electrode 136 (Fig. 10) and the first semiconductor layers 106 (Fig. 10) to form vertically-spaced nanostructures 108 (Fig. 11, paragraph 0115, wherein “semiconductor nanolayers 108”) from the second semiconductor layers 108 (Fig. 10); and
forming a metal gate line 194 (Fig. 11, paragraph 0117) surrounding the vertically-spaced nanostructures 108 (Fig. 11).
Xie does not disclose patterning a mask over the metal gate line, wherein an opening in the mask is located over a region of the metal gate line;
etching through the opening to form a trench through the metal gate line; and
depositing an isolation material in the trench to form an isolation feature separating a first metal gate structure from a second metal gate structure.
Tsai discloses patterning a mask 172 (Fig. 9, paragraph 0035) over the metal gate line 110 (Fig. 9, paragraph 0035), wherein an opening 113 (Fig. 9, paragraph 0035) in the mask 172 (Fig. 9) is located over a region of the metal gate line 110 (Fig. 9);
etching through the opening 113 (Fig. 9) to form a trench 113 (Fig. 10) through the metal gate line 110 (Fig. 10); and
depositing an isolation material 114 (Fig. 11, paragraph 0035) in the trench 113 (Fig. 10) to form an isolation feature 114 (Fig. 11) separating a first metal gate structure (left 110 in Fig. 11) from a second metal gate structure (right 110 in Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie to include patterning a mask over the metal gate line, wherein an opening in the mask is located over a region of the metal gate line; etching through the opening to form a trench through the metal gate line; and depositing an isolation material in the trench to form an isolation feature separating a first metal gate structure from a second metal gate structure, as taught by Tsai, since a cut metal gate process (Tsai, paragraph 0011) refers to a fabrication process where after a metal gate (e.g., a high-k metal gate or HK MG) replaces a dummy gate structure (e.g., a polysilicon gate), the metal gate is cut (e.g., by an etching process) to separate the metal gate into two or more portions such that each portion (Tsai, paragraph 0011) functions as a metal gate for an individual transistor.
Regarding claim 22, Xie further discloses the method of claim 21, wherein the trench extends into a shallow trench isolation region 104 (Fig. 10, paragraph 0050) underlying the metal gate line 136 (Fig. 10).
Regarding claim 23, Xie in view of Tsai discloses the method of claim 21, however Xie does not disclose forming a gate cap over the metal gate line before patterning the mask, wherein etching through the opening comprises etching through the gate cap and through the metal gate line.
Tsai discloses forming a gate cap 170 (Fig. 8, paragraph 0040) over the metal gate line 110 (Fig. 8, paragraph 0040) before patterning the mask 172 (Fig. 9, paragraph 0035), wherein etching through the opening 113 (Fig. 9, paragraph 0035) comprises etching through the gate cap 170 (Fig. 10) and through the metal gate line 110 (Fig. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie to include forming a gate cap over the metal gate line before patterning the mask, wherein etching through the opening comprises etching through the gate cap and through the metal gate line, as taught by Tsai, since the patterned hard mask layers 170 and 172 (Tsai, Fig. 10, paragraph 0036) protect the rest of the high-k metal gate 112 (Tsai, Fig. 10, paragraph 0036) from the etching process.
Regarding claim 24, Xie further discloses the method of claim 21, wherein depositing the isolation material 180 (Fig. 10) in the trench 173 (Fig. 10) comprises conformally (see “CVD” in paragraph 0111) depositing the isolation material 180 (Fig. 10) to enclose an air gap 181 (Fig. 10) within the isolation feature 180 (Fig. 10).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813